Semiconductor Contact Hole Patterning with Low-Aspect-Ratio Masks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device fabrication lies in reducing process defects and simplifying integration techniques for highly integrated devices, particularly in forming fine patterns which require new and costly exposure techniques.
Innovation Solution
A method involving the formation of device isolation layers, conductive layers, and mask patterns, where second mask patterns are grown using an inductively coupled plasma process with alternating source and etching gases, and an etch-back process is performed to form storage node contacts and capacitors, reducing the aspect ratio of mask patterns and preventing leaning issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If new exposure techniques are used to form fine patterns, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The mask pattern formation process is segmented into multiple stages: first mask patterns are formed using conventional photolithography, then second mask patterns are grown on top using atomic layer deposition (ALD). This segmentation allows each stage to use optimized techniques, avoiding the need for expensive new exposure techniques while achieving fine pattern precision.
Solution Approach 2:
The invention transitions from two-dimensional planar patterning to three-dimensional vertical structuring by growing second mask patterns vertically on top of first mask patterns. This vertical dimension enables fine pattern formation through controlled deposition thickness rather than relying solely on advanced photolithography resolution.
2Manufacturing precision
If mask pattern thickness is increased to prevent leaning, then manufacturing precision is improved, but aspect ratio increases making fabrication more difficult
Solution Approach 1:
Instead of increasing mask pattern thickness in the vertical direction alone, the invention uses a two-layer stacked structure where thin first mask patterns provide lateral coverage and thin second mask patterns grown on top provide vertical protection. This distributes the protective function across two dimensions, maintaining low aspect ratios while preventing leaning.
Solution Approach 2:
The mask pattern structure uses composite construction with first mask patterns (formed by photolithography) and second mask patterns (grown by ALD) having different material properties and formation mechanisms. This composite structure achieves the protective function against leaning while maintaining manufacturability through complementary strengths of each layer type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the semiconductor device fabrication process, reduces defects, and enhances integration density by minimizing the aspect ratio of mask patterns, thereby preventing leaning problems and improving the efficiency of pattern formation.
Implementation Method 1
growing second mask patterns may be performed by an inductively coupled plasma (ICP) method
Implementation Method 2
growing the second mask patterns may include alternately and repeatedly supplying a source gas and an etching gas into the same process chamber
Implementation Method 3
performing an etch-back process on the conductive material to form storage node contacts
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.