Contact Hole Fabrication via Segmented Etching and Dielectric Sidewall Coating

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Solution Overview

Problem

The existing methods for forming contact holes in semiconductor devices face challenges such as impaired contact profiles due to low etching selectivity, polymer residue issues, and contact-to-contact bridges caused by seam formation between adjacent gate electrodes, especially at feature sizes below 0.065 micrometers.

Innovation Solution

A method involving a semiconductor substrate with an etch stop layer and dielectric layers, where the dielectric layer and etch stop layer are patterned to form openings, followed by the deposition of a dielectric thin film on the sidewalls and exposed substrate, and subsequent removal of the thin film to prevent seam issues and improve contact hole profiles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If in-situ etching of ILD layer and CESL layer is performed without removing photoresist, then etching process is simplified, but polymer residue causes tapered profile and increases contact sheet resistance

Engineering Contradiction:
Improveetching process simplicityVSAvoidcontact hole profile
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the etching process into two distinct stages: first etching the ILD layer while photoresist is present, then removing photoresist and etching the CESL layer. This segmentation prevents polymer residue from affecting the second etching step, thereby maintaining contact hole profile precision while still simplifying the overall manufacturing process compared to complete photoresist removal before etching.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary etching of the ILD layer while photoresist is still in place, utilizing the photoresist as a temporary protective mask. This preliminary action allows the photoresist to prevent polymer residue formation during the first etching step, and the photoresist is subsequently removed before the second etching step to prevent interference with CESL layer etching.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If low etching selectivity between ILD layer and CESL layer is used, then etching process is faster, but contact profile is impaired

Engineering Contradiction:
Improveetching speedVSAvoidcontact profile
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the etching process into two separate operations with different selectivity requirements. The first etching step targets the ILD layer with optimized parameters for that specific layer, and the second etching step targets the CESL layer after photoresist removal. This segmentation allows each etching step to use parameters optimized for speed without compromising the overall contact profile, as each step contributes to a different portion of the final structure.

Inventive Principle:
Principle #1Segmentation

3Length of moving object

If feature size is reduced to 0.045 micrometers or less, then device miniaturization is achieved, but CESL layer merges and causes seam issue leading to contact-to-contact bridge

Engineering Contradiction:
Improvefeature sizeVSAvoidseam issue
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent extracts and removes the photoresist layer between the etching of the ILD layer and the etching of the CESL layer. This extraction serves multiple purposes: it removes the source of polymer residue that could cause seam formation, and it allows for fresh etching conditions when etching the CESL layer at reduced feature sizes, thereby preventing the merging and seam issues that would otherwise occur during miniaturization.

Inventive Principle:
Principle #2Taking out (Extraction)

4Device complexity

If photoresist layer is used as etching hard mask for both ILD and CESL layers, then process steps are reduced, but polymer residue produces tapered profile

Engineering Contradiction:
Improveprocess stepsVSAvoidcontact hole profile
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent segments the photoresist usage into two distinct phases: first as a protective mask during ILD layer etching, then removed and used again as a mask for CESL layer etching. This segmented approach maintains the simplicity of using photoresist as the primary mask material while eliminating the polymer residue problem by removing the photoresist between etching steps, thereby preserving contact hole profile precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary etching of the ILD layer while photoresist is present, utilizing the photoresist as a temporary protective mask. This preliminary action allows the photoresist to prevent polymer residue formation during the first etching step, and the photoresist is subsequently removed before the second etching step to prevent interference with CESL layer etching and avoid tapered profiles in the final contact holes.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces contact sheet resistance, prevents contact-to-contact bridges by blocking seams with a dielectric thin film, and maintains the contact hole profile integrity, effectively addressing the limitations of prior art in micro-miniaturization.

Implementation Method 1

forming a dielectric thin film covering the dielectric layer, sidewalls of the openings, and the exposed semiconductor substrate

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS8236702B2Method of fabricating openings and contact holes
Publication Date: 2012.08.07 MARLIN SEMICON LTD
  • US8236702B2 patent drawing
  • US8236702B2 patent drawing
  • US8236702B2 patent drawing

AI summary

A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.