Power Semiconductor Contact Hole Layout for Reliable Source Implantation

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Solution Overview

Problem

Defects in semiconductor source regions during the manufacturing of power semiconductor devices can go undetected at the wafer level, leading to unreliable devices, and existing methods do not adequately ensure the correct formation and connection of semiconductor source and body regions.

Innovation Solution

A new mesa region formation process involving tilted source implantation and a resist layer to form semiconductor source and body regions, ensuring reliable electrical connections and efficient functionality, particularly in devices with pattern trench structures where source and gate electrodes are closely adjacent.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional source region formation processes are used, then manufacturing simplicity is maintained, but defect detection capability is insufficient and manufacturing precision deteriorates

Engineering Contradiction:
Improvesource region formation precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The source region formation process is segmented into multiple sequential steps: forming the insulation layer with contact hole, performing tilted ion implantation to create the source region, and forming the metal contact. This segmentation allows each step to be optimized independently, improving manufacturing precision while maintaining overall process manageability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The insulation layer is formed in advance before source region formation, and the contact hole is created as a preliminary structure. The tilted ion implantation angle is predetermined to achieve the desired source region profile. These preliminary actions enable better control over the final source region geometry and reduce defects

Inventive Principle:
Principle #10Preliminary action

2Reliability

If wafer-level inspection methods are used, then manufacturing speed is maintained, but defect detection capability is insufficient

Engineering Contradiction:
Improvedevice reliabilityVSAvoidmanufacturing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The process creates clearly defined structural features (insulation layer with contact hole, tilted source region) that serve as built-in indicators for subsequent inspection. The specific geometric characteristics make defects more detectable in later testing stages, improving reliability without requiring additional real-time monitoring equipment that would reduce throughput

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If tilted source implantation is used, then manufacturing precision is improved, but process complexity increases

Engineering Contradiction:
Improvesource region positioning precisionVSAvoidprocess ease of manufacture
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The insulation layer acts as an intermediary structure that simplifies the tilted implantation process. By providing a well-defined contact hole and surface structure, it serves as a natural mask and alignment reference, making the complex tilted implantation step more controllable and easier to manufacture with standard equipment

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This process enhances the detection of defects and ensures reliable implementation of semiconductor regions, reducing the likelihood of manufacturing errors and improving the overall reliability and efficiency of power semiconductor devices.

Implementation Method 1

subjecting the semiconductor body region of the second conductivity type to a tilted source implantation using the at least one contact hole at least partially as a mask basis for forming a semiconductor source region of a first conductivity type in the mesa region

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS11949006B2Power semiconductor device with p-contact and doped insulation blocks defining contact holes
Publication Date: 2024.04.02 INFINEON TECH DRESDEN GMBH & CO KG
  • US11949006B2 patent drawing
  • US11949006B2 patent drawing
  • US11949006B2 patent drawing

AI summary

A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.