Contact Hole Formation in Stacked Memory Devices
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Solution Overview
Problem
The formation of high aspect ratio holes in stacked type memory devices becomes difficult as the bit density increases, leading to wider joint portions and increased parasitic capacitance between semiconductor or conductive members.
Innovation Solution
The formation of contact holes is divided into two stages, with the uppermost portion being enlarged to form recesses for insulating members, allowing for the creation of contacts with a level difference that reduces parasitic capacitance by using insulating members with different compositions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of holes is increased to increase bit density, then the bit density is improved, but the formation of holes becomes difficult
Solution Approach 1:
The hole formation process is divided into two separate etching steps: first forming initial holes through the stacked body, then forming upper holes that connect to these initial holes. This segmentation allows each etching step to work with more manageable aspect ratios while achieving the overall high aspect ratio needed for increased bit density
Solution Approach 2:
The first etching step preliminarily forms holes through the stacked body before the second etching step connects them to the upper surface. This preliminary action creates a foundation that makes the final high aspect ratio hole formation feasible by breaking down the single complex etching step into two manageable steps
2Length of stationary object
If the formation of holes is divided into two to form high aspect ratio holes, then the aspect ratio is improved, but the joint portions of holes become wide
Solution Approach 1:
The insulating film is selectively formed only in specific regions: on the side surfaces of the stacked body and in the joint portions between upper holes and initial holes. This local quality approach allows precise control of the joint portion dimensions, maintaining narrow connections where needed while providing insulation where required
Solution Approach 2:
The insulating film acts as an intermediary material that is deposited in the joint portions between upper holes and initial holes. This intermediary layer allows the two etching steps to be connected while controlling the joint portion width, preventing direct metal-to-metal contact and reducing parasitic capacitance
3Ease of manufacture
If the joint portions of holes become wide, then the hole formation becomes easier, but the parasitic capacitance between semiconductor members increases
Solution Approach 1:
The insulating film serves as a mediator material filled in the joint portions between upper holes and initial holes. This intermediary insulating layer electrically isolates adjacent conductive members, preventing direct capacitive coupling and thereby reducing parasitic capacitance while still allowing the holes to be formed with manageable dimensions
Solution Approach 2:
The insulating film is selectively applied in the joint portions where parasitic capacitance would occur, providing localized electrical isolation exactly where needed. This local quality approach targets the specific problem area without requiring insulation throughout the entire structure, maintaining ease of manufacture while reducing parasitic capacitance
Data Source
AI summary
An integrated circuit device includes an insulating film, a contact extending in a first direction and being provided inside the insulating film, and an insulating member. A composition of the insulating member is different from a composition of the insulating film. A level difference is formed in a side surface of the contact, a portion of a region of the side surface other than the level difference contacts the insulating film. The insulating member contacts the level difference.