Semiconductor Contact Hole Stop Conduction Layer Etch Control
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Solution Overview
Problem
In semiconductor device manufacturing, the punch-through phenomenon during etching of lower metal layers leads to variations in contact resistance and reduced yield, especially in highly-integrated devices, where increasing the thickness of lower metal layers is limited and can result in voids during IMD oxide film deposition.
Innovation Solution
A method involving the formation of a contact hole stop conduction layer using tungsten, platinum, ruthenium, iridium, and copper, which acts as an etch mask to minimize etching of the lower metal layer, allowing for precise etching and deposition of subsequent layers to reduce contact resistance variations and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of the lower metal layer is increased to prevent punch-through etching, then etching margin is improved, but the amount of etching increases and voids may be generated during IMD oxide film deposition
Solution Approach 1:
A contact hole stop conduction layer is introduced as an intermediary layer between the lower metal layer and the IMD oxide film. This stop conduction layer serves as a mediator that provides etch selectivity, allowing the etch process to stop precisely at the desired depth without penetrating into the lower metal layer, thereby eliminating the need to increase lower metal layer thickness while preventing void formation.
Solution Approach 2:
The invention changes the etching parameters by introducing a layer with different etch selectivity properties. The contact hole stop conduction layer has specific etch selectivity characteristics that allow controlled etching depth, enabling precise termination of the etch process before reaching the lower metal layer, thus avoiding both punch-through and void formation.
2Reliability
If the thickness of the lower metal layer is increased to obtain sufficient punch through margins, then contact resistance variation is reduced, but device integration is limited and etching amount increases
Solution Approach 1:
The contact hole stop conduction layer acts as an intermediary that provides the necessary etch selectivity and depth control, replacing the need to increase lower metal layer thickness. This allows maintaining reliable contact resistance while enabling higher device integration density and reducing the overall etching burden.
3Manufacturing precision
If the lower metal layer thickness is increased, then punch through margin is improved, but the etching process removes more material and subsequent IMD oxide film deposition cannot fully bury the etched portions, generating voids
Solution Approach 1:
The contact hole stop conduction layer serves as a protective intermediary that prevents excessive etching into the lower metal layer. By providing etch selectivity, it ensures the etch process stops at the correct depth, preserving the lower metal layer material and preventing the formation of voids during subsequent IMD oxide film deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes variations in contact resistance between upper and lower metal layers, enhances etching margins, and improves gap-fill margins during IMD oxide film deposition, thereby increasing the yield of semiconductor devices during mass production.
Implementation Method 1
forming a contact hole stop conduction layer on the lower metal layer; forming a photoresist pattern on the contact hole stop conduction layer, and then etching and patterning the contact hole stop conduction layer and the lower metal layer using the photoresist pattern as an etch mask
Implementation Method 2
depositing an IMD oxide film on the entire structure, and then performing a photolithography and etch process on the IMD oxide film to form a second contact hole
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a semiconductor substrate on which a plurality of transistors are defined; forming a wiring pattern over the transistors, the wiring pattern contacting at least one transistor; depositing a first oxide film over the wiring pattern; defining a first contact hole on the oxide film, the first contacting hole exposing the wiring pattern; forming a lower metal layer having a first barrier metal layer, a first metal layer and a second barrier metal layer over the oxide film, the lower metal layer filling the first contact hole; forming a contact hole stop conduction layer over the lower metal layer; depositing a second oxide film over the contact hole stop conduction layer; etching a selected portion of the second oxide film to form a hole exposing the contact hole stop conduction layer; etching the exposed contact hole stop layer to define a second contact hole; forming a contact plug within the second contact hole, the contact plug contacting the lower metal layer; and forming an upper metal layer including a third barrier metal layer and a second metal layer, the upper metal layer contacting the contact plug.