Source/Drain Contact Isolation Features for Parasitic Capacitance
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, achieving adequate electrical isolation between source/drain contacts becomes increasingly challenging, leading to performance issues such as increased parasitic capacitance.
Innovation Solution
The formation of isolation features with a void between source/drain contacts, utilizing a 'cut last' or 'cut first' process, where a shared source/drain contact is divided and isolation features are formed between the separated contacts, achieving a low relative permittivity and enhanced electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but electrical isolation between source/drain contacts deteriorates leading to increased parasitic capacitance
Solution Approach 1:
The isolation feature incorporates a void (porous structure) between source/drain contacts to reduce the relative permittivity of the isolation material. This void structure allows the isolation feature to maintain physical separation while minimizing parasitic capacitance, enabling continued scaling without the harmful capacitive coupling that would otherwise result from reduced feature sizes.
Solution Approach 2:
The isolation feature acts as an intermediary structure between source/drain contacts, using a low-k material with void content to mediate the electrical isolation. This intermediary approach provides adequate electrical isolation even when contacts are in close proximity due to reduced feature sizes, thus preventing increased parasitic capacitance while maintaining high integration density.
2Object-generated harmful factors
If isolation features are formed with voids to reduce parasitic capacitance, then electrical isolation between source/drain contacts improves, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The low-k isolation material is deposited and patterned before the source/drain contacts are fully formed. This preliminary action allows the isolation feature structure to be established in advance, simplifying subsequent contact formation steps and reducing overall manufacturing complexity despite the added isolation feature requirements.
Solution Approach 2:
The void structure within the isolation feature is formed by nesting a lower-permittivity material (or vacuum) within the isolation material matrix. This nested structure achieves the low-k effect without requiring completely separate void formation processes, thereby reducing manufacturing complexity while still achieving reduced parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the electrical isolation between source/drain contacts, reducing parasitic capacitance and improving the performance of FinFETs, particularly in high-voltage difference applications like SRAM cells.
Implementation Method 1
achieving a low relative permittivity and enhanced electrical isolation
Data Source
AI summary
In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.