Contact Jumper Layout Above Gate Lines for Compact FinFET Cells

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor processes shrink, the reduction in fin pitch leads to smaller active regions in standard cells, complicating the design and layout of integrated circuits, particularly in finFETs, making it difficult to maintain a minimal height and size while avoiding interference between contact jumpers and gate contacts.

Innovation Solution

The integration of T-shaped or inverted T-shaped contact jumpers that cross gate lines above active regions, allowing for reduced interference and enabling simpler layout of gate contacts, vias, and metal patterns, thereby maintaining a minimal height and reducing the overall size of the integrated circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the fin pitch is reduced to meet smaller design rules, then the integration density is improved, but the active region footprint becomes smaller making layout more difficult

Engineering Contradiction:
Improveintegration densityVSAvoidlayout complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The contact jumper is configured to extend in the second direction (longitudinal direction) above the gate line, transitioning from a planar arrangement to a three-dimensional structure that utilizes the vertical dimension. This allows the contact jumper to span across gate lines without increasing the lateral footprint of the active region, thereby maintaining high integration density while simplifying layout complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the standard cell height is reduced to minimize circuit size, then the overall circuit footprint is improved, but interference between contact jumpers and gate contacts becomes more difficult to avoid

Engineering Contradiction:
Improvecircuit footprintVSAvoidinterference between contact jumpers and gate contacts
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The contact jumper is positioned above the gate line in the vertical dimension rather than in the same lateral plane as gate contacts. This three-dimensional arrangement allows the contact jumper to cross over gate lines without lateral interference, enabling reduced standard cell height while avoiding harmful interference between different circuit elements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The contact jumper structure acts as an intermediary element that mediates between the need for compact layout and the requirement to avoid interference. By extending in the second direction above the gate line, it provides a pathway for electrical connection that does not conflict with gate contact positions, thus resolving the interference issue while maintaining compact dimensions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If contact jumpers are positioned to cross gate lines, then routing flexibility is improved, but interference with gate contacts increases

Engineering Contradiction:
Improverouting flexibilityVSAvoidinterference with gate contacts
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The contact jumper extends in the second direction above the gate line, utilizing the vertical dimension to achieve routing flexibility. This allows the contact jumper to cross over gate lines and connect different regions while maintaining lateral separation from gate contacts, thus providing routing adaptability without causing interference.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12456663B2Integrated circuit having contact jumper
Publication Date: 2025.10.28 SAMSUNG ELECTRONICS CO LTD
  • US12456663B2 patent drawing
  • US12456663B2 patent drawing
  • US12456663B2 patent drawing

AI summary

An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.