Contact Structure Lattice Alignment for Low Resistance
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Solution Overview
Problem
Existing contact structures in power transistors exhibit high contact resistance, leading to significant power loss due to on-state resistance, which is not adequately reduced by conventional film compositions and thicknesses, even with optimized selections.
Innovation Solution
The formation of conductive structures with aligned crystal lattices between the semiconductor layer and the conductive material, using specific metals like Ti, Zr, and Hf, and adjusting the relative Al content and thickness of the bulk conductive film to achieve low lattice mismatch and coherent interfaces, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional film compositions and thicknesses are used in contact structures, then manufacturing is simpler, but contact resistance remains high leading to significant power loss
Solution Approach 1:
The contact structure employs a multi-layer composite design comprising a first conductive layer (e.g., Ti, Zr, or Hf) directly contacting the semiconductor layer, a second conductive layer (e.g., Al or Al alloy) as the bulk conductive film, and optionally a third conductive layer. This composite structure reduces contact resistance by combining materials with complementary properties: the first layer provides low contact resistance through lattice matching, while the second layer provides high bulk conductivity.
Solution Approach 2:
The invention systematically varies critical parameters including the thickness of each conductive layer, the aluminum content in Al alloy layers (e.g., Al95Si3Cu2), and the selection of specific metals (Ti, Zr, Hf) to optimize the balance between contact resistance and power loss. By adjusting these parameters, the contact structure achieves minimal contact resistance while controlling overall power consumption.
2Reliability
If the bulk conductive film thickness is increased, then conductivity improves, but contact resistance may not be sufficiently reduced and device complexity increases
Solution Approach 1:
The contact structure applies local quality by assigning different functions to different layers: the first conductive layer (5-50 nm thick) is optimized for low contact resistance at the interface with the semiconductor layer through lattice matching, while the second conductive layer (50-500 nm thick) provides bulk conductivity. This localized optimization allows each layer to perform its specific function efficiently without requiring uniform thickness or composition throughout.
Solution Approach 2:
The bulk conductive film is segmented into multiple distinct layers with different materials and thicknesses rather than using a single uniform layer. This segmentation allows independent optimization of each layer's properties - the first layer for interface contact resistance and the second layer for bulk conductivity - thereby achieving superior overall performance that cannot be obtained with a single-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly lowers contact resistance, reducing on-state resistance (Rdson) and energy loss in power transistors, particularly in high electron mobility transistors, by ensuring epitaxial or fiber texture alignment and optimal Al phase distribution.
Implementation Method 1
aligned crystal lattices between the semiconductor layer and the conductive material, using specific metals like Ti, Zr, and Hf, and adjusting the relative Al content and thickness of the bulk conductive film to achieve low lattice mismatch and coherent interfaces
Data Source
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AI summary
An electronic device can include a semiconductor layer and a contact structure forming an ohmic contact with the layer. In an embodiment, the semiconductor layer can include a III-N material, and the contact structure includes a first phase and a second phase, wherein the first phase includes Al, the second phase includes a metal, and the first phase contacts the semiconductor layer. In another embodiment, the semiconductor layer can be a monocrystalline layer having a surface along a crystal plane. The contact structure can include a polycrystalline material including crystals having surfaces that contact the surface of the monocrystalline layer, wherein a lattice mismatch between the surface of the monocrystalline layer and the surfaces of the crystals is at most 20%.