Continuous Contact Liner Stress Engineering for Semiconductor Devices

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Solution Overview

Problem

Conventional semiconductor devices face challenges in reducing the area of the np boundary region, leading to increased chip size and reduced yield due to overlapping contact liners and void formation, which can cause short-circuits and affect transistor characteristics.

Innovation Solution

A semiconductor device design where the n-channel contact liner has a shrinkage force and the p-channel contact liner has an expansion force, formed continuously to apply stress to the channels, reducing the np boundary region area and preventing voids, with a manufacturing method involving ion implantation and heat treatment to adjust the stress of the contact liner film.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact liners are formed separately in N-channel and P-channel regions using conventional DSL technology, then stress can be applied to improve transistor mobility, but the contact liners overlap in the np boundary region causing increased area, void formation, and reduced yield

Engineering Contradiction:
Improvetransistor mobilityVSAvoidnp boundary region control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent combines the formation of n-channel and p-channel contact liners into a single continuous contact liner structure. By forming one continuous liner instead of separate overlapping liners, the invention eliminates the overlap problem in the np boundary region while maintaining stress application capabilities for both transistor types through localized stress-inducing layers.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the continuous contact liner into different functional regions by introducing stress-inducing layers at specific locations. The contact liner itself is continuous, but localized stress is applied to the n-channel region and p-channel region separately through stress-inducing layers, achieving differentiated stress control without overlapping liner formation.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If the np boundary region area is reduced to improve chip size, then manufacturing cost decreases, but yield is reduced due to overlapping contact liners and void formation

Engineering Contradiction:
Improvechip sizeVSAvoidcontact liner alignment
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent merges the n-channel and p-channel contact liners into a single continuous structure that spans both regions. This eliminates the need for precise alignment of separate liners and prevents overlap in the np boundary region, allowing for reduced chip area without compromising manufacturing precision or yield.

Inventive Principle:
Principle #5Merging (Combining)

3Force

If contact liners overlap in the np boundary region, then stress application is maintained, but voids form causing short-circuits and affecting transistor characteristics

Engineering Contradiction:
Improvestress applicationVSAvoidshort-circuit prevention
Core Design Contradiction:
ForceVSReliability

Solution Approach 1:

The patent combines overlapping contact liners into a single continuous contact liner. This continuous structure maintains stress application to both n-channel and p-channel transistors through localized stress-inducing layers while eliminating the gaps and voids that would cause short-circuits in overlapping configurations.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves channel mobility in both n-channel and p-channel transistors without using special materials, reduces the np boundary region width, and enhances yield by minimizing voids and short-circuit risks, allowing for smaller chip size and improved design flexibility.

Implementation Method 1

an n-channel contact liner formed over the first active region and side surfaces and a top surface of the n-channel gate and having a shrinkage force

Methodology Applied
Scientific EffectFilm shrinkage: Thermal Contraction

Implementation Method 2

a p-channel contact liner formed over the second active region and side surfaces and a top surface of the p-channel gate, formed continuously with the n-channel contact liner so as to have a larger thickness than that of the n-channel contact liner, and having an expansion force

Methodology Applied
Scientific EffectFilm expansion: Thermal Expansion

Implementation Method 3

a manufacturing method involving ion implantation and heat treatment to adjust the stress of the contact liner film

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 4

a manufacturing method involving ion implantation and heat treatment to adjust the stress of the contact liner film

Methodology Applied
Scientific EffectHeat treatment: Heat Treatment

Data Source

PatentUS8084826B2Semiconductor device and manufacturing method thereof
Publication Date: 2011.12.27 ADVANCED INTEGRATED CIRCUIT PROCESS LLC
  • US8084826B2 patent drawing
  • US8084826B2 patent drawing
  • US8084826B2 patent drawing

AI summary

An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.