Semiconductor Contact Liner Layout for Via-to-Gate Spacing
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Solution Overview
Problem
As semiconductor devices shrink in scale, challenges arise in improving the via-to-gate overlay window and time-dependent dielectric breakdown (TDDB) window, which affects the reliability of the devices due to close spacing between the gate via and source/drain contact.
Innovation Solution
The formation of a semiconductor device structure involves creating a first mask layer covering the gate stack, followed by a second mask layer that protects the first mask layer during etching, ensuring a greater spacing between the gate via and source/drain contact, thereby improving the via-to-gate overlay window and TDDB window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between gate via and source/drain contact is reduced to improve device density, then device density increases, but the via-to-gate overlay window and TDDB window deteriorate
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and spacer layers before the actual via formation. The mandrel is positioned at a first location and spacers are formed around it, creating a predetermined spacing structure that ensures adequate distance between the gate via and source/drain contact before any etching or via formation occurs. This preliminary structuring prevents overlay issues and maintains TDDB windows while still achieving high device density through precise spatial arrangement.
Solution Approach 2:
The patent uses an intermediary mandrel structure that is eventually removed after serving its purpose. The mandrel acts as a temporary mediator that defines the spacing between gate via and source/drain contact during fabrication. By using this intermediary structure, the patent achieves precise spacing control without requiring direct alignment between the via and contact, thus improving overlay window while maintaining device density.
2Reliability
If the spacing between gate via and source/drain contact is increased to improve overlay window and TDDB window, then via-to-gate overlay window and TDDB window improve, but device density decreases
Solution Approach 1:
The patent resolves the spacing-density contradiction by transitioning from two-dimensional planar spacing to three-dimensional vertical stacking. The mandrel structure extends in the vertical dimension, allowing the gate via and source/drain contact to be positioned at different vertical levels while maintaining adequate horizontal spacing. This dimensional transition enables sufficient spacing for improved overlay window and TDDB window without sacrificing device density, as the spacing requirement is met in the vertical dimension rather than consuming horizontal space.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a transistor on a substrate, a contact electrically connected to a source/drain feature of the transistor, a first dielectric layer on a gate stack of the transistor, a second dielectric layer on the contact, a gate spacer layer between the gate stack of the transistor and the contact, and a contact liner between the gate spacer layer and the contact. A top of the contact liner is located higher than a bottom surface of the second dielectric layer and lower than a top surface of the second dielectric layer.