Semiconductor Contact Openings with Dielectric Liner Shrink
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Solution Overview
Problem
As semiconductor devices become smaller, forming accurate patterns in layers becomes increasingly difficult due to the limitations of current pattern transfer methods, which can lead to manufacturing defects and reduced functionality, especially for features like vias and conductive lines in interconnect structures.
Innovation Solution
A method involving the deposition of a dimension offset liner material (DOLM) in the openings of dielectric layers to adjust the dimensions of contact openings, allowing for the formation of smaller features than previously possible with standard lithography tools, thereby increasing the process window and reducing manufacturing complexity and defectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard lithography tools are used to form patterns, then manufacturing process is simpler, but manufacturing precision deteriorates for features smaller than current tool capabilities
Solution Approach 1:
The pattern transfer process is divided into multiple steps: first forming a mandrel pattern, then using it to define opening locations, removing the mandrel, and finally forming the actual patterns in the openings. This segmentation allows each step to be optimized independently, achieving sub-lithography dimensions without requiring more complex lithography tools.
Solution Approach 2:
A mandrel pattern is formed in advance before the actual pattern transfer. This preliminary mandrel structure serves as a template that guides subsequent processing steps, enabling precise positioning of openings and patterns at dimensions smaller than what standard lithography can directly achieve.
2Productivity
If feature dimensions are reduced to increase device density, then productivity improves, but manufacturing precision deteriorates due to pattern transfer limitations
Solution Approach 1:
A dimension offset liner material is deposited as an intermediary layer between the opening structure and the final conductive material. This liner acts as a mediator that precisely controls the interface dimensions, enabling accurate pattern formation at sub-lithography dimensions and maintaining manufacturing precision while supporting higher device density.
3Reliability
If conventional pattern transfer methods are used, then manufacturing process is simpler, but reliability deteriorates due to manufacturing defects
Solution Approach 1:
The manufacturing process is segmented into distinct steps with clear intermediates: mandrel formation, opening definition, mandrel removal, and pattern formation. Each step produces a verifiable intermediate structure, allowing for defect detection and correction at multiple stages, thereby improving overall manufacturing reliability despite increased process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of semiconductor device features with dimensions as small as 5 nanometers, improving manufacturing reliability and reducing the risk of defects, while maintaining performance specifications, by extending the capabilities of existing lithography tools.
Implementation Method 1
A method involves depositing a dimension offset liner material (DOLM) in openings of dielectric layers
Data Source
AI summary
A method of making a semiconductor device includes forming a conductive element over a substrate, depositing a layer of dielectric material over the conductive element, etching the layer of dielectric material to define an opening, where a dimension of the opening adjacent the conductive element has a first width measured in a direction parallel to a top surface of the substrate, reducing the first width by depositing a dielectric liner in the opening, etching the dielectric liner to expose a portion of the conductive element, where a dimension of the conductive element exposed has a second width less than the first width, depositing a conductive material in the opening, where the dielectric layer is between the conductive material and the layer of dielectric material, and the conductive material is electrically connected to the conductive element.