Contact Plug Etching Through CESL With Selective Breakthrough
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Solution Overview
Problem
As semiconductor devices approach smaller feature sizes, challenges arise in the etching process for hardmasks and etch stop layer removal, particularly in the middle end of line process for the 3 nm node, where precise control and selectivity are needed to maintain integration density and prevent damage to underlying structures.
Innovation Solution
A breakthrough etching process involving dopant implantation and selective etch stop removal is employed, using physical or chemical implantation to modify the etch rate and selectivity, allowing for precise exposure of conductive features while minimizing lateral etching and maintaining the profile of the opening, with the use of recess chemicals and ion beam acceleration to remove the etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for hardmask and etch stop layer removal, then the etching can proceed through the layers, but the etch rate cannot be precisely controlled and selectivity is poor, causing damage to underlying conductive features and adjacent dielectric layers
Solution Approach 1:
The patent applies preliminary action by performing dopant implantation into the etch stop layer before the etching process. This pre-treatment modifies the etch rate and selectivity of the etch stop layer, enabling precise control of the etching process and preventing damage to underlying conductive features and adjacent dielectric layers during subsequent etching operations.
Solution Approach 2:
The patent changes the physical or chemical parameters of the etch stop layer through dopant implantation. By introducing dopants that modify the material properties, the etch rate and selectivity are altered to achieve precise etching control, allowing the etch process to stop at the desired location without damaging underlying structures.
2Reliability
If the etch stop layer is removed to expose conductive features, then interconnect formation can proceed, but lateral etching occurs that damages adjacent dielectric layers and compromises structural integrity
Solution Approach 1:
The patent performs dopant implantation as a preliminary action to modify the etch stop layer's etching characteristics before the actual etching process. This ensures that when the etch stop layer is removed to expose conductive features for interconnect formation, the modified etch rate and selectivity prevent lateral etching that would damage adjacent dielectric layers and compromise structural integrity.
Solution Approach 2:
The patent applies local quality by selectively modifying the etch stop layer properties through dopant implantation. The dopant concentration and distribution are controlled to create localized changes in etch rate and selectivity, ensuring precise etching at the target location while protecting adjacent dielectric layers from lateral etching damage.
3Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but the etching process becomes less selective and harder to control
Solution Approach 1:
The patent changes the physical or chemical parameters of the etch stop layer through controlled dopant implantation. By adjusting dopant concentration, energy, and distribution, the etch rate and selectivity are optimized for advanced node dimensions, maintaining precise etching control even as feature sizes are reduced to increase integration density.
Solution Approach 2:
The patent applies preliminary dopant implantation to prepare the etch stop layer for subsequent etching at advanced nodes. This pre-treatment ensures that even at reduced feature sizes, the etching process maintains the necessary selectivity and control to achieve the required integration density without sacrificing manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables efficient and precise removal of the etch stop layer, exposing conductive features without significant damage to adjacent dielectric layers, thereby supporting the formation of reliable interconnects and maintaining the structural integrity of semiconductor devices at advanced node sizes.
Implementation Method 1
performing a dopant implantation in the target region
Implementation Method 2
ion beam acceleration to remove the etch stop layer
Data Source
AI summary
Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.