Conductive Contact Plug with Diffusion Barrier for Semiconductor Memory
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving low resistance and preventing surface roughness and heat-induced migration during the fabrication of memory circuits, which affects their performance and reliability.
Innovation Solution
The semiconductor device includes a conductive contact plug with a stack of a low-resistance structure and a planarizing layer, comprising a diffusion barrier layer, a low-resistance material layer, and a gap-fill layer, which are designed to reduce resistance and prevent metal ion diffusion and surface deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a simple conductive structure is used, then fabrication is easier, but resistance is high and reliability is poor
Solution Approach 1:
The contact plug is segmented into multiple functional layers: a diffusion barrier layer to prevent metal ion diffusion, a low-resistance material layer to reduce electrical resistance, and a planarizing layer to provide surface planarity. Each layer performs a specific function, collectively improving reliability without requiring excessive complexity.
Solution Approach 2:
The contact plug employs a composite structure combining different materials with complementary properties: tungsten or copper for low resistance, titanium nitride or tantalum for diffusion barrier properties, and silicon oxide or silicon nitride for planarization. This composite approach achieves high reliability by leveraging the strengths of each material.
2Manufacturing precision
If metal ion diffusion is not prevented, then fabrication is simpler, but surface roughness increases and device performance deteriorates
Solution Approach 1:
The diffusion barrier layer acts as an intermediary between the metal contact and the semiconductor substrate, preventing metal ion diffusion while allowing electrical conduction. This intermediate layer protects the substrate from contamination and maintains surface planarity without requiring complex fabrication processes.
Solution Approach 2:
The planarizing layer is applied locally over the contact plug region to provide surface planarity only where needed, rather than planarizing the entire substrate. This localized approach maintains manufacturing precision at the critical contact area while minimizing additional process complexity.
3Reliability
If resistance is not reduced, then structure is simpler, but electrical conductivity is poor and device performance is limited
Solution Approach 1:
The low-resistance material layer is designed with specific thickness parameters (typically 50-200 nm) and material composition (tungsten or copper) to optimize electrical conductivity. By controlling the resistance parameter through material selection and dimensional design, high electrical conductivity is achieved without excessive structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electrical conductivity and reliability of the semiconductor device by reducing resistance and preventing surface roughness and heat-induced migration, facilitating easier fabrication and improved performance in memory circuits.
Implementation Method 1
the low-resistance structure includes a diffusion barrier layer, a low-resistance material layer, and a gap-fill layer
Implementation Method 2
The low-resistance structure includes a diffusion barrier layer, a low-resistance material layer, and a gap-fill layer
Data Source
AI summary
Implementations of the disclosed technology provide an electronic device including a semiconductor memory and a method for fabricating the same, in which processes are easily performed and the characteristics of a variable resistance element are improved. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate; a conductive contact plug formed over the first conductive layer and including a stack of a conductive low-resistance structure and a conductive planarizing layer; and a variable resistance pattern coupled to the contact plug, wherein the low-resistance structure comprises a diffusion barrier layer, a low-resistance material layer and a gap-fill layer.