Semiconductor Contact Plug Structure With Etch-Stop Leakage Control
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining high electrical performance and reducing leakage between gate stacks and conductive features.
Innovation Solution
The formation of contact plug structures involves an etch stop layer with high etch selectivity over gate masks, allowing for the creation of conductive features with various shapes that improve electrical connection and reduce resistance, while minimizing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but leakage between gate stacks and conductive features increases
Solution Approach 1:
The patent divides the dielectric layer into multiple segments: a first dielectric layer with a first etch rate and a second dielectric layer with a second etch rate. This segmentation allows selective removal of material to form contact holes without etching the gate mask, thereby preventing leakage while maintaining high integration density through miniaturized features.
Solution Approach 2:
The patent introduces an intermediary etch stop layer between the gate mask and the dielectric layers. This intermediary layer has an etch rate intermediate between the gate mask and the dielectric layers, acting as a buffer that stops the etching process before reaching the gate mask, thus preventing direct contact and potential leakage between conductive features and gate stacks.
2Ease of manufacture
If conventional single-layer dielectric structure is used, then manufacturing is simpler, but etching control precision deteriorates due to inability to selectively remove dielectric material without affecting gate mask
Solution Approach 1:
The dielectric structure is segmented into multiple layers with different etch rates, enabling selective removal of specific dielectric material while preserving the gate mask. This segmentation provides precise etching control during contact hole formation, allowing the etch process to stop at the desired depth without damaging the gate mask.
Solution Approach 2:
The patent changes the etch rate parameter by using dielectric layers with different compositions and etch characteristics. The first dielectric layer has a first etch rate and the second dielectric layer has a second etch rate, allowing the etching process to be controlled with high precision by selecting appropriate etch conditions for each layer.
3Productivity
If gate mask is directly exposed during etching, then etching process is faster, but leakage between gate stacks and conductive features occurs
Solution Approach 1:
The patent applies preliminary action by forming the etch stop layer and configuring the multi-layer dielectric structure before the etching process. This preliminary configuration ensures that during the high-speed etching process, the etch stop layer and selective dielectric layers prevent direct exposure of the gate mask, thereby maintaining fast etching speed while preventing leakage.
Solution Approach 2:
The etch stop layer serves as an intermediary that prevents direct contact between the etching process and the gate mask. This intermediary layer allows the etching to proceed quickly through the dielectric layers while stopping before reaching the gate mask, thus maintaining high productivity without causing leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance of semiconductor devices by improving the connection between source/drain contact plugs and conductive features, while reducing leakage and allowing for a variety of conductive feature shapes.
Implementation Method 1
an etch stop layer with high etch selectivity over gate masks
Implementation Method 2
conductive features with various shapes that improve electrical connection and reduce resistance
Data Source
AI summary
A method includes forming an epitaxial source/drain region in a substrate; forming a first inter-layer dielectric over the epitaxial source/drain region; forming a gate stack over the substrate and adjacent to the first inter-layer dielectric; forming a gate mask over the gate stack; forming a source/drain plug through the first inter-layer dielectric and electrically connected to the epitaxial source/drain region; depositing a dielectric layer over the gate mask and the first inter-layer dielectric, the dielectric layer having a different etch selectivity than the gate mask; forming a second inter-layer dielectric over the dielectric layer; etching an opening through the second inter-layer dielectric and the dielectric layer, the opening exposing the source/drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature being electrically connected to the source/drain plug.