Contact Plug Structure With Dielectric Spacers for Gate Isolation

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Solution Overview

Problem

The formation of metal gates and contact plugs in transistors is complex and costly due to the need for etching back metal gates and forming hard masks, which increases the aspect ratio of openings and can lead to parasitic capacitance and electrical shorting.

Innovation Solution

A method involving the formation of replacement gate stacks without etching back metal gates and using low-k and high-k dielectric spacers to reduce parasitic capacitance, along with the integration of contact plugs that penetrate through multiple insulating layers, reducing the need for hard masks and simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If metal gates are etched back and hard masks are formed, then contact plugs can be formed, but the aspect ratio of openings increases and parasitic capacitance occurs

Engineering Contradiction:
Improvecontact plug formationVSAvoidopening aspect ratio
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

Dielectric spacers are formed around the metal gate before contact plug formation, preliminarily establishing the isolation structure. This preliminary action prevents the need for subsequent hard mask formation and etching back operations, thereby maintaining lower aspect ratios throughout the process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Dielectric spacers act as intermediary structures between the metal gate and the contact plugs. These spacers provide the necessary isolation and define the contact opening boundaries without requiring hard masks, thus controlling the aspect ratio while enabling contact plug formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If metal gates are etched back and hard masks are formed, then contact plugs can be formed, but parasitic capacitance and electrical shorting occur

Engineering Contradiction:
Improvecontact plug formationVSAvoidelectrical isolation
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Dielectric spacers serve as intermediary isolation structures positioned between the metal gate and contact plugs. These spacers prevent direct electrical contact where it should not occur, eliminating parasitic capacitance and preventing electrical shorting while still allowing proper contact plug formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric spacer material is strategically placed only in specific locations around the metal gate where isolation is needed. This localized application provides electrical isolation precisely where required without affecting other areas, preventing parasitic capacitance and electrical shorting.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If complex processes with hard masks are used, then contact plugs can be formed, but manufacturing costs increase

Engineering Contradiction:
Improvecontact plug formationVSAvoidmanufacturing process
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The formation of dielectric spacers is merged with the existing metal gate formation process. The same spacer deposition and patterning steps that define the metal gate also define the contact openings, eliminating the need for separate hard mask formation and removal steps, thereby reducing manufacturing complexity and cost.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The dielectric spacers serve multiple functions: they define the metal gate boundaries, provide electrical isolation, and define the contact opening locations. This multi-functionality eliminates the need for separate hard masks and reduces the overall number of process steps, lowering manufacturing complexity and cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12464751B2Contact plugs and methods forming same
Publication Date: 2025.11.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12464751B2 patent drawing
  • US12464751B2 patent drawing
  • US12464751B2 patent drawing

AI summary

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.