Semiconductor Contact Plug Structure for Gate Leakage Isolation
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, reducing minimum feature sizes lead to increased challenges such as leakage between source/drain contact plugs and adjacent gate stacks, affecting electrical performance and requiring improved dielectric layer schemes for enhanced integration density and process window expansion.
Innovation Solution
A method involving the formation of a plurality of dielectric layers with different materials over gate stacks to reduce leakage between source/drain contact plugs and adjacent gate stacks, allowing for improved electrical performance and enlarged etch and lithography process windows, including the use of oxygen-containing dielectric layers and specific material combinations for optimized semiconductor device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but leakage between source/drain contact plugs and adjacent gate stacks increases
Solution Approach 1:
The dielectric layer is segmented into multiple distinct layers (first dielectric layer and second dielectric layer) with different materials and etch selectivities. This segmentation allows selective etching to form contact plugs that stop at the gate stack, preventing leakage while maintaining high integration density through miniaturization.
Solution Approach 2:
The first dielectric layer acts as an intermediary layer between the second dielectric layer and the gate stack. This intermediate layer with different etch selectivity enables precise control of the etching process, allowing contact plugs to be formed that terminate at the gate stack interface without penetrating into it, thus preventing electrical leakage.
2Productivity
If minimum feature sizes are reduced to improve integration density, then manufacturing capacity increases, but process window for etching and lithography decreases
Solution Approach 1:
The patent changes the material parameters of the dielectric layers to achieve different etch selectivities. By selecting materials with appropriate etch rate ratios (greater than 1:5), the process window for etching is expanded, allowing precise formation of contact plugs even at reduced minimum feature sizes, thereby maintaining ease of manufacture while improving integration density.
3Device complexity
If single dielectric layer is used to simplify structure, then device complexity is reduced, but leakage control between contact plugs and gate stacks deteriorates
Solution Approach 1:
The dielectric structure is segmented into multiple layers with distinct materials. The first dielectric layer has different etch selectivity compared to the second dielectric layer, enabling selective etching to form contact plugs that precisely terminate at the gate stack. This segmentation provides superior leakage control compared to a single dielectric layer while maintaining manageable device complexity.
Solution Approach 2:
Different regions of the dielectric structure have different material compositions and etch selectivities. The first dielectric layer in contact with the gate stack has specific material properties that enable precise etching control, while the second dielectric layer has different properties optimized for other functions. This local quality differentiation achieves excellent leakage control without excessive overall complexity.
Data Source
AI summary
A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.