Contact Plug Formation via Inhibiting Layer Deposition

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Solution Overview

Problem

The formation of contact plugs with high aspect ratios in semiconductor integrated circuit devices often results in voids and seams due to structural characteristics of deep contact holes, which deteriorate electrical characteristics of interconnection layers.

Innovation Solution

A method involving the formation of a nucleation layer, a semi-bulk layer, and an inhibiting layer within the contact hole, followed by a main bulk layer deposition, where the inhibiting layer, comprising tungsten nitride, is used to control the growth rate of the contact plug, preventing voids and seams by delaying deposition on the upper surface of the contact hole.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If a deep contact hole is formed to achieve high aspect ratio contact plug, then the contact plug can meet high integration needs, but voids and seams are generated in the contact plug

Engineering Contradiction:
Improvecontact hole depthVSAvoidcontact plug quality
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The contact plug formation process is divided into multiple stages with different deposition rates: an initial fast deposition stage to quickly build up material, followed by a slow deposition stage to ensure uniform filling without voids. This segmentation of the deposition process allows the contact hole to be filled properly while maintaining the required depth, resolving the contradiction between deep contact hole formation and defect-free contact plug quality.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If gap-filling is performed in deep contact hole, then contact plug can be formed, but voids and seams are generated due to structural characteristics

Engineering Contradiction:
Improvecontact plug formationVSAvoidelectrical characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The deposition rate is dynamically adjusted during the contact plug formation process. The process starts with a fast deposition rate to efficiently fill the deep contact hole, then transitions to a slow deposition rate to ensure uniform material distribution and eliminate voids and seams. This dynamic control of deposition parameters enables both easy manufacture of contact plugs and maintenance of reliable electrical characteristics.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of contact plugs in deep contact holes without voids or seams, thereby improving the electrical characteristics of interconnection layers by ensuring uniform deposition and reducing defects.

Implementation Method 1

A semi-tungsten layer may be formed on the tungsten nucleation layer. The semi-tungsten layer and the exposed tungsten nucleation layer may be treated using a nitrogen radical to form an inhibiting layer.

Methodology Applied
Scientific EffectChemical Vapor Deposition: Chemical Vapour Deposition

Data Source

PatentUS11482452B2Method of forming a contact plug in a semiconductor integrated circuit device
Publication Date: 2022.10.25 WONIK IPS CO LTD
  • US11482452B2 patent drawing
  • US11482452B2 patent drawing
  • US11482452B2 patent drawing

AI summary

In a method of forming a contact plug in a semiconductor integrated circuit device, the contact plug may be formed in a process chamber of a substrate-processing apparatus. The process chamber may have a process space. The process chamber may include a substrate supporter placed in a lower region of the process space to support a semiconductor substrate, and a gas injector placed in an upper region of the process space to inject a gas to the semiconductor substrate. An insulating interlayer having a contact hole may be formed on the semiconductor substrate loaded into the process space. A nucleation layer may be formed on an inner surface of the contact hole and an upper surface of the insulating interlayer. A semi-bulk layer may be formed on the nucleation layer in a lower region of the contact hole. An inhibiting layer may be formed on the semi-bulk layer and the exposed nucleation layer. A main-bulk layer may be formed on the semi-bulk layer to fill the contact hole with the main-bulk layer.