3D Memory Contact Plug Layout for Defect-Resistant Interconnects
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity beyond two-dimensional arrangements, necessitating innovative three-dimensional memory cell configurations.
Innovation Solution
A semiconductor device design incorporating a lower structure with circuit interconnection patterns at different height levels, a vertical memory structure penetrating through wordlines, and a contact plug connecting bitlines and wordlines, with specific insulating layers to prevent defects and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell configurations are implemented to increase data storage capacity, then storage density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangements to three-dimensional configurations by stacking wordlines and creating vertical memory structures that penetrate through multiple wordline layers. This dimensional change enables increased storage capacity by utilizing the vertical space above the substrate, allowing memory cells to be arranged in three dimensions rather than confined to a single plane.
Solution Approach 2:
The vertical memory structures are nested within the stacked wordline configuration, with the memory structures penetrating through multiple insulating layers and wordlines. This nesting approach allows the memory cells to be integrated within the three-dimensional interconnection structure, maximizing space utilization while maintaining organizational order.
2Reliability
If multiple insulating layers with different materials are used to prevent defects and improve contact resistance, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs different insulating materials in specific locations within the interlayer insulating structure. The first insulating material is used in regions requiring high breakdown voltage to prevent defects, while the second insulating material with lower dielectric constant is used in other regions to reduce parasitic capacitance and improve contact resistance. This localized material selection optimizes performance for specific functional requirements.
Solution Approach 2:
The interlayer insulating structure is formed as a composite of two different insulating materials stacked in specific configurations. This composite structure combines the advantages of both materials: the first material provides high breakdown voltage for defect prevention, while the second material provides low dielectric constant for improved electrical performance. The composite approach enables simultaneous achievement of multiple performance goals.
Data Source
AI summary
A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.