Contact Plug Structure for Narrow-Pitch Memory Stack Etching
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Solution Overview
Problem
As semiconductor memory devices shrink in size, the challenges of maintaining the integrity and functionality of increasingly narrow line widths pose difficulties in semiconductor process technology, particularly in the manufacturing of memory devices where precise patterning and protection of stack structures are critical.
Innovation Solution
The solution involves forming a memory device with stack structures on a substrate, covered by a protective layer and contact plugs, where the protective layer conformally covers the stack structures and the contact plugs are designed with a narrower and wider portion to maintain the shape and resistance of the plugs during etching processes, and the use of multiple patterning processes to ensure accurate placement and reliability of the conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the line width in semiconductor memory devices is reduced to increase integration, then the device size becomes smaller and integration density increases, but the manufacturing precision and reliability of the device deteriorate due to challenges in maintaining integrity of narrow line widths
Solution Approach 1:
A protective layer is formed conformally over the stack structures before the contact hole etching process. This preliminary protective action prevents damage to the stack structures during subsequent etching operations, addressing the manufacturing precision challenges associated with narrow line widths while maintaining the reduced device size for high integration density
2Device complexity
If conventional contact plug structures are used in reduced-size devices, then the manufacturing process is simpler, but the contact plug resistance and reliability deteriorate due to the smaller dimensions
Solution Approach 1:
The contact plug is designed with an asymmetric cross-sectional shape featuring a wider portion and a narrower portion. The wider portion provides a larger contact area to reduce resistance and improve reliability, while the narrower portion maintains compatibility with the reduced device dimensions. This asymmetric design resolves the contradiction between simple manufacturing and reliable performance in miniaturized devices
Solution Approach 2:
The contact plug structure exhibits local quality variations with different cross-sectional dimensions at different locations. The wider portion is positioned where high current density occurs to reduce resistance, while the narrower portion accommodates space constraints in the miniaturized device structure
3Reliability
If the protective layer is formed conformally over stack structures, then the stack structures are protected from damage during etching, but the manufacturing process complexity increases due to additional process steps
Solution Approach 1:
The conformal protective layer is formed to extend over the top surfaces of the stack structures, providing self-aligned protection that automatically adapts to the stack structure geometry. This self-service approach ensures comprehensive protection during etching operations while the conformal nature of the layer formation keeps the process relatively simple, balancing reliability improvement with manufacturing complexity
Data Source
AI summary
Provided is a memory device including a substrate, a plurality of stack structures, a protective layer, and a plurality of contact plugs. The stack structures are disposed over the substrate. The protective layer conformally covers top surfaces and sidewalls of the stack structures. The contact plugs are respectively disposed over the substrate between the stack structures. One of the contact plugs includes a narrower portion and a wider portion over the narrower portion. In a top view, the wider portion is separated from an adjacent protective layer by a distance.