Contact Plug Upper Pattern for Lower-Resistance MOSFET Scaling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices are scaled down, the reduction in size leads to deteriorated operating characteristics, particularly in MOSFETs, due to increased electrical resistance and integration challenges.

Innovation Solution

A semiconductor device design featuring a contact plug with a unique upper pattern that protrudes from the interlayer insulating layer, having a wider lower region than upper region, which reduces electrical resistance by preventing the line barrier pattern from extending into the interlayer insulating layer, thereby improving electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If MOSFETs are scaled down to reduce device size, then device integration density is improved, but electrical resistance increases and operating characteristics deteriorate

Engineering Contradiction:
Improvedevice sizeVSAvoidoperating characteristics
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The contact plug structure is modified locally by adding an upper pattern with a protrusion that has a wider lower region than upper region. This local structural change concentrates the current flow path and reduces electrical resistance at the contact plug, thereby improving operating characteristics without changing the overall device size.

Inventive Principle:
Principle #3Local quality

2Reliability

If the contact plug structure is modified to reduce electrical resistance, then electrical characteristics are improved, but device complexity increases

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidcontact plug structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The upper pattern of the contact plug is designed with an asymmetric protrusion structure where the lower region width is greater than the upper region width. This asymmetric geometry optimizes current distribution and reduces electrical resistance while maintaining manufacturing feasibility through standard photolithography and etching processes.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS11869836B2Method for forming a semiconductor device
Publication Date: 2024.01.09 SAMSUNG ELECTRONICS CO LTD
  • US11869836B2 patent drawing
  • US11869836B2 patent drawing
  • US11869836B2 patent drawing

AI summary

A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.