Contact Rail Layout for Backside Power Delivery in GAA Transistors
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Solution Overview
Problem
Existing integrated circuit designs face challenges in efficiently providing power to header cells through power rails, particularly in gate-all-around transistors, leading to inefficiencies and voltage drops.
Innovation Solution
A semiconductor structure with contact rails is developed, connecting backside power rails to source and drain regions of gate-all-around transistors, utilizing CMG regions to cut gate stacks and form perpendicular contact rails, enabling efficient power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power is provided through traditional power rails in header cells, then power distribution is achieved, but voltage drops and inefficiencies occur
Solution Approach 1:
The patent introduces contact rails extending in a first direction (perpendicular to gate stacks) connected to backside power rails, while source/drain contact plugs extend in a second direction (parallel to gate stacks). This dimensional change creates a three-dimensional power distribution network that reduces current path length and resistance, thereby reducing voltage drops and improving power distribution efficiency compared to traditional planar power rails
Solution Approach 2:
The contact rails serve as intermediary conductive structures that connect backside power rails to source/drain regions through contact plugs. This intermediary structure provides optimized current pathways that reduce resistance and voltage drop compared to direct lateral power rail connections, effectively mediating the power transfer from backside to active regions
2Productivity
If CMG regions are used to cut gate stacks and form contact rails, then power distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The CMG (cut-metal-gate) regions serve multiple functions: they electrically isolate adjacent gate stacks, provide structural support for contact rail formation, and create defined pathways for power distribution. By making the CMG regions multi-functional, the patent improves power distribution efficiency without proportionally increasing device complexity, as the same structural elements perform multiple roles
Solution Approach 2:
The gate stacks are segmented by CMG regions that extend between them, creating discrete electrical isolation zones. This segmentation enables the formation of contact rails in the CMG regions without interfering with gate operation, allowing efficient power distribution while maintaining manageable device complexity through modular structural division
Data Source
AI summary
A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.