Semiconductor Contact Structure for Single-Step CMP Planarity
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Solution Overview
Problem
Chemical mechanical polishing (CMP) processes in semiconductor device fabrication often result in stress cracking and material dishing, leading to surface non-planarity, thickness variations, and increased yield loss, particularly in 3D NAND flash memory devices, due to the use of two-step CMP processes which are complex, time-consuming, and costly.
Innovation Solution
A single-step CMP process is employed using a first conductive layer thinner than the second dielectric layer, where the second dielectric layer has similar hardness to the first dielectric layer, reducing stress and the likelihood of cracking, and eliminating the need for a two-step process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a two-step CMP process is used to remove materials and achieve planar surfaces, then surface planarity is improved, but the process becomes complex, time-consuming, and costly while causing stress cracking and material dishing
Solution Approach 1:
The patent combines two separate CMP steps into a single integrated CMP process. The first dielectric layer and second dielectric layer are polished together in one step, eliminating the need for separate polishing operations. This merging reduces process complexity, decreases manufacturing time, and lowers costs while maintaining surface planarity through proper material selection and polishing parameter optimization.
Solution Approach 2:
The patent changes the hardness parameter of the second dielectric layer to be similar to that of the first dielectric layer. This parameter adjustment ensures uniform material removal rates during the single-step CMP process, preventing stress cracking and material dishing that occur when materials have significantly different hardness values. The hardness matching allows both layers to be polished simultaneously without compromising surface quality.
2Loss of substance
If a two-step CMP process is used to remove materials, then material removal is achieved, but processing time and cost increase
Solution Approach 1:
The patent merges the removal of the first dielectric layer and second dielectric layer into a single CMP operation. By selecting materials with similar hardness properties, both layers can be polished in one step rather than requiring sequential polishing operations. This significantly reduces processing time and associated costs while achieving the necessary material removal for device fabrication.
3Loss of substance
If materials with different hardness are used in CMP, then material removal occurs, but stress cracking and dishing increase
Solution Approach 1:
The patent fundamentally changes the hardness parameter relationship between the first dielectric layer and second dielectric layer. Instead of using materials with significantly different hardness values, the patent selects a second dielectric layer material whose hardness closely matches that of the first dielectric layer. This hardness matching ensures uniform stress distribution during polishing, preventing stress cracking and material dishing while enabling effective material removal in a single CMP step.
Solution Approach 2:
The patent applies the principle of local quality by ensuring that the second dielectric layer has locally matched hardness properties to the first dielectric layer at their interface. This localized hardness matching at the material interface prevents stress concentration and cracking that would occur with mismatched hardness values, while still allowing for effective material removal during the CMP process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes crack formation during CMP, reduces processing time and cost, and maintains surface planarity by using a majority of the second dielectric material for polishing, which has hardness closer to the first dielectric layer, thereby addressing the issues of stress cracking and dishing.
Implementation Method 1
CMP can be viewed as a hybrid of chemical etching and free abrasive polishing
Implementation Method 2
CMP can be viewed as a hybrid of chemical etching and free abrasive polishing
Data Source
AI summary
Aspects of the disclosure provide a semiconductor device. The semiconductor device can include a trench formed in a first dielectric layer, a trench filler layer that fills a portion of the trench, a conductive layer over the trench filler layer, and a second dielectric layer over the conductive layer. The second dielectric layer is disposed in the trench. The semiconductor device can also include a contact structure configured to connect to the conductive layer through a hole in the second dielectric layer.