Contact Trench Structure Using Al-Containing Dielectric Selectivity
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in achieving reliable interconnects with reduced resistance and capacitance as dimensions scale down, particularly due to issues with oxidation and over etching during the formation of contact trenches.
Innovation Solution
Incorporating an aluminum-containing dielectric layer with specific compositions and properties, such as Al, O, and N, to provide high etching selectivity and protect underlying features from oxidation, along with a cap layer to reduce contact resistance and improve adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional aluminum metallurgy is used for interconnections, then manufacturing process is simpler, but resistance component of RC time delay increases
Solution Approach 1:
The patent changes the material parameter from traditional aluminum metallurgy to copper metallurgy, which has lower resistivity. This parameter change directly reduces the resistance component of RC time delay while maintaining compatibility with existing damascene manufacturing processes through modified deposition and CMP steps
2Device complexity
If conventional etching processes are used to form contact trenches, then process complexity is lower, but oxidation of underlying features occurs and etching precision deteriorates
Solution Approach 1:
The patent applies a cap layer deposition step before the etching process to preliminarily protect the underlying conductive features from oxidation during subsequent processing. This preliminary protective action prevents oxidation damage while the etching process forms the contact trenches with improved precision
Solution Approach 2:
The cap layer acts as an intermediary protective barrier between the etching environment and the underlying conductive features. This intermediary layer prevents direct contact between oxygen/moisture and the copper interconnections, eliminating oxidation while allowing the etching process to proceed with high precision
3Productivity
If dimensions are scaled down to increase functional density, then production efficiency improves, but manufacturing precision requirements increase and reliability problems arise
Solution Approach 1:
The patent employs copper metallurgy with lower resistivity than aluminum, which compensates for the increased resistance effects that occur at scaled-down dimensions. This material parameter change allows continued scaling while maintaining electrical performance and manufacturing precision
Solution Approach 2:
The patent uses a composite structure consisting of copper interconnections embedded in a low-k dielectric material matrix. This composite approach provides both the low resistance needed for scaled dimensions and the mechanical support required for manufacturing precision, while the low-k material reduces capacitance effects that become significant at smaller geometries
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The aluminum-containing dielectric layer enhances etching precision, reduces contact resistance, and prevents oxidation, thereby improving the reliability and performance of integrated circuits as they scale down.
Implementation Method 1
protect underlying features from oxidation
Implementation Method 2
reduce contact resistance
Data Source
AI summary
The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.