Contact Trenches for Strain Transfer in Closely Spaced Transistors
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Solution Overview
Problem
Conventional techniques for creating stressed dielectric layers in semiconductor devices face inefficiencies when transistor dimensions are scaled, leading to process non-uniformities and reduced performance due to limited conformal deposition capabilities.
Innovation Solution
The solution involves adjusting the size and design of contact elements in the dielectric material surrounding the gate electrode structures to enhance strain transfer mechanisms, using contact trenches that extend along the transistor width direction for one type of transistor, while conventional contact elements are used for the other type, allowing for efficient strain induction and reduced complexity in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional contact elements are used in closely spaced transistors, then manufacturing process is simple, but strain transfer efficiency is insufficient and performance enhancement is limited
Solution Approach 1:
The contact element is segmented into distinct regions: a first contact portion extending under the first transistor and a second contact portion extending under the second transistor. This segmentation allows each contact portion to independently transfer strain to its respective transistor, improving strain transfer efficiency while maintaining a relatively simple overall structure that can be integrated into existing manufacturing processes.
Solution Approach 2:
The contact element exhibits local quality variations through its different portions, where each contact portion is optimized for its specific location and function. The first contact portion is configured to transfer strain to the first transistor while the second contact portion serves the second transistor, allowing localized optimization of strain transfer without requiring complete redesign of the entire contact structure.
2Strength
If a thicker stress-inducing dielectric layer is used, then strain induction capability is enhanced, but process complexity increases due to additional etch stop layers
Solution Approach 1:
The dielectric layer is designed to serve multiple functions simultaneously: it acts as both the stress-inducing layer that generates strain in the channel regions and as the etch stop layer that prevents over-etching during contact hole formation. This multi-functionality allows the use of a thicker dielectric layer to enhance strain induction capability without requiring additional separate layers, thereby avoiding increased process complexity.
Solution Approach 2:
The patent merges the stress-inducing dielectric layer and the etch stop layer into a single integrated layer. This combination eliminates the need for separate etch stop layers that would otherwise be required when using thicker stress-inducing layers, thus enhancing strain induction capability while maintaining relatively simple process flows without additional layer deposition or removal steps.
3Speed
If transistor dimensions are scaled down, then operating speed increases, but strain transfer uniformity deteriorates due to limited conformal deposition capabilities
Solution Approach 1:
The contact element extends in the lateral dimension beneath the transistors, creating a three-dimensional strain transfer pathway. This dimensional approach allows strain to be transferred uniformly across the channel regions even when transistors are closely spaced, overcoming the limitations of conformal deposition techniques that struggle to maintain uniformity at reduced dimensions. The lateral extension provides an additional dimension for strain distribution.
Solution Approach 2:
The contact element serves as an intermediary structure that mediates strain transfer from the dielectric layer to the channel regions of closely spaced transistors. This intermediary contact structure ensures uniform strain distribution across multiple transistors by providing a consistent mechanical coupling pathway, thereby maintaining manufacturing precision and strain transfer uniformity even when transistor dimensions are scaled down and spacing is reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the scalability of strain-inducing mechanisms, reduces unwanted strain components, and improves transistor performance by allowing a thicker stress-inducing dielectric layer without additional etch stop layers, simplifying the process flow and increasing yield.
Implementation Method 1
The conductivity of the channel region may be enhanced by increasing a mobility of charge carriers in the channel region. For example, creating tensile strain in the channel region of a silicon layer may increase the mobility of electrons. The lattice structure in the channel region may be modified, for instance, by creating tensile or compressive strain therein
Implementation Method 2
creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons
Data Source
AI summary
Scalability of a strain-inducing mechanism on the basis of a stressed dielectric overlayer may be enhanced by forming a single stress-inducing layer in combination with contact trenches, which may shield a significant amount of a non-desired stress component in the complementary transistor, while also providing a strain component in the transistor width direction when the contact material may be provided with a desired internal stress level.