Source/Drain Contact-to-Via Structure for Etch-Variation Reliability
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Solution Overview
Problem
The reliability of the connection between source/drain contacts and through vias in semiconductor devices is compromised due to differences in etching amounts between the upper interlayer insulating layer and the gate cut, leading to potential connection failures.
Innovation Solution
A connection portion is introduced within the upper interlayer insulating layer, connecting the source/drain contact to the through via, with a wider width than the source/drain contact, to enhance the reliability of the connection and mitigate etching-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a direct connection between source/drain contact and through via is formed, then the structure is simple, but the connection reliability is poor due to etching amount differences
Solution Approach 1:
The patent introduces a connection portion as an intermediary element between the source/drain contact and the through via. This connection portion compensates for etching amount differences by having its bottom surface positioned at a different level than the direct contact interface, thereby ensuring reliable electrical connection despite variations in etching depths of the upper interlayer insulating layer and gate cut.
2Reliability
If the connection portion has the same width as the source/drain contact, then the manufacturing process is simpler, but the connection reliability is insufficient
Solution Approach 1:
The patent applies local quality by making the connection portion wider than the source/drain contact in specific regions. This localized width increase provides better etching compensation and connection reliability at the critical interface between the contact and through via, while maintaining a more standard dimensions elsewhere in the structure.
Data Source
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AI summary
A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on an upper surface of the substrate, a field insulating layer surrounding a sidewall of the active pattern on the upper surface of the substrate, a first gate electrode extending in a second horizontal direction intersecting the first horizontal direction on the active pattern, a source/drain region disposed on at least one side of the first gate electrode on the active pattern, an upper interlayer insulating layer covering the source/drain region on the field insulating layer, a through via penetrating through the substrate, the field insulating layer and the upper interlayer insulating layer in a vertical direction, the through via spaced apart from the source/drain region in the second horizontal direction, a source/drain contact disposed inside the upper interlayer insulating layer on at least one side of the first gate electrode, the source/drain contact connected to the source/drain region, and a connection portion disposed inside the upper interlayer insulating layer, the connection portion connected to each of the through via and the source/drain contact, wherein a width of the connection portion in the first horizontal direction is greater than a width of the source/drain contact in the first horizontal direction.