Contact Via Layout With Liner-Protected Gate Isolation
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Solution Overview
Problem
In integrated chip manufacturing, the challenge is to maintain reliable isolation between the contact via and the gate electrode while preventing the spacer structure from being removed during the etching process, which is exacerbated by the increasing difficulty in dimension and overlay control as feature sizes decrease, leading to potential device failure and high leakage current.
Innovation Solution
The introduction of a liner layer over the spacer structure, composed of a material more resistant to etching than the spacer, which reduces exposure time and prevents removal during the etching process, and the use of a sacrificial layer to prevent direct contact with the gate electrode, thereby maintaining isolation and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacer structure is directly exposed during etching to form contact via, then the etching process can proceed efficiently, but the spacer structure may be removed leading to loss of isolation between contact via and gate electrode
Solution Approach 1:
A liner layer is introduced as an intermediary between the spacer structure and the etching process. This liner layer is selectively removed to expose the gate electrode for contact via formation, while the spacer structure remains protected. The liner layer acts as a sacrificial protective barrier that enables efficient etching without compromising the spacer structure's isolation function.
2Area of stationary object
If feature sizes are decreased to increase functional density, then more devices can be integrated per chip area, but interference amongst features increases and dimension control becomes more difficult
Solution Approach 1:
The liner layer is formed over the spacer structure before the etching process begins. This preliminary protective action ensures that when the etching process is subsequently performed to create contact vias, the spacer structure is already protected and will not be inadvertently removed, even as feature dimensions shrink and processing tolerances tighten.
3Ease of manufacture
If the liner layer is removed completely to expose the gate electrode, then contact via formation is simplified, but the spacer structure loses its protective barrier and may be damaged
Solution Approach 1:
The liner layer is selectively removed only in the specific region where contact via formation is required, rather than being completely removed. This localized removal exposes the gate electrode contact area while preserving the liner layer's protective function over the spacer structure in other regions, thereby simplifying contact via formation without compromising spacer structure integrity.
Data Source
AI summary
In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a gate electrode over a substrate. The gate electrode is laterally separated from a dielectric by a spacer structure. A sacrificial layer is formed over a top surface of the gate electrode. A liner layer is formed along a sidewall of the spacer structure and on the sacrificial layer. The sacrificial layer is removed and a hard mask material is formed over the gate electrode. A part of the dielectric is removed to form a contact opening laterally separated from the gate electrode by the spacer structure. A conductive contact is formed within the contact opening.