Contact Via Structure With Liner-Protected Gate Isolation
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Solution Overview
Problem
As feature sizes in integrated chips decrease, interference between semiconductor device features increases, leading to challenges in maintaining effective isolation and preventing device failure due to improper coupling and high leakage current.
Innovation Solution
The introduction of a liner layer over the spacer structure, composed of a material more resistant to etching than the spacer, prevents exposure and removal of the spacer during etching processes, thereby maintaining isolation and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are decreased to increase functional density, then the number of semiconductor devices per chip area increases, but interference amongst features increases leading to device failure
Solution Approach 1:
The patent applies segmentation by dividing the isolation structure into multiple components: a spacer structure and a liner layer. The liner layer is deposited over the spacer structure to provide additional isolation functionality. This segmented approach enhances the isolation effect between closely spaced features, preventing interference while maintaining high functional density.
Solution Approach 2:
The liner layer acts as an intermediary element between the spacer structure and the contact via. It provides a protective barrier that prevents direct interaction between the etchant and the spacer structure, while also ensuring proper electrical isolation. This intermediary layer resolves the contradiction by enabling closer feature spacing without compromising device reliability.
2Reliability
If a liner layer is introduced over the spacer structure to prevent exposure during etching, then isolation reliability is improved, but device structure complexity increases
Solution Approach 1:
The liner layer is deposited over the spacer structure before the etching process to prevent exposure and removal of the spacer during etching. This preliminary protective action ensures that the spacer structure maintains its integrity and isolation function throughout subsequent manufacturing steps, improving isolation reliability without requiring complex post-processing corrections.
Solution Approach 2:
The patent changes the material parameter of the isolation structure by introducing a liner layer with different etch resistance properties than the spacer structure. This parameter change enables the liner layer to protect the spacer during etching processes, enhancing isolation reliability while adding only a thin protective layer rather than a complex structural modification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The liner layer effectively protects the spacer structure from etching, ensuring reliable isolation between the contact via and the gate electrode, while also reducing contact resistance and maintaining device reliability.
Implementation Method 1
a liner layer over the spacer structure, the liner layer comprising a material more resistant to etching than the spacer
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.