Self-Aligned Contact Via Structure With Snaking CESL

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Solution Overview

Problem

The semiconductor industry faces challenges in forming reliable and low-resistance contact vias due to poor etch selectivity between different hard mask layers, leading to short-circuit paths and unintentional thinning of mask layers, especially with the scaling of IC dimensions, which affects device reliability and increases manufacturing complexity.

Innovation Solution

A method is introduced that uses a self-aligned contact via with an enlarged critical dimension, employing a single hard mask layer and a snaking contact etch stop layer (CESL) to form contact vias, eliminating the need for multiple hard mask layers and reducing the risk of voltage breakdown, thereby improving etch selectivity and avoiding additional chemical mechanical polishing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple hard mask layers are used to form contact vias, then etch selectivity is improved, but device complexity and manufacturing process complexity increase

Engineering Contradiction:
Improveetch selectivityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the second hard mask layer from the conventional process, using only the first hard mask layer combined with a self-aligned contact etch stop layer. This eliminates the complexity of managing multiple hard mask layers while maintaining etch selectivity through the self-aligned CESL approach.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The self-aligned contact etch stop layer automatically positions itself at the correct location through conformal deposition on the first hard mask layer, eliminating the need for additional alignment steps and processes that would be required with multiple hard mask layers.

Inventive Principle:
Principle #25Self-service

2Manufacturing precision

If multiple hard mask layers are used, then contact via formation is achieved, but unintentional thinning of mask layers occurs due to additional CMP processes

Engineering Contradiction:
Improvecontact via formationVSAvoidmask layer thinning
Core Design Contradiction:
Manufacturing precisionVSLoss of substance

Solution Approach 1:

The patent removes the second hard mask layer and its associated CMP process, using only the first hard mask layer with self-aligned CESL. This eliminates the source of unintentional mask layer thinning while still achieving precise contact via formation through the self-aligned approach.

Inventive Principle:
Principle #2Taking out (Extraction)

3Manufacturing precision

If additional CMP processes are used for multiple hard mask layers, then manufacturing precision is maintained, but manufacturing time and cost increase

Engineering Contradiction:
Improvemask layer thickness controlVSAvoidmanufacturing cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent extracts and eliminates the additional CMP process that would be required for a second hard mask layer. The self-aligned CESL approach maintains manufacturing precision without requiring this time-consuming additional step, thereby reducing overall manufacturing cycle time.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in more reliable, low-resistance contact vias with a large critical dimension, reducing manufacturing costs and enhancing device reliability by eliminating the need for additional hard mask layers and associated process steps, while protecting the metal gate sidewall spacer from voltage breakdown.

Implementation Method 1

performing a contact via etching process to form a contact via opening in the dielectric layer and to expose a portion of the CESL in the trench

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

forming a dielectric layer over the CESL

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS12074063B2Contact formation method and related structure
Publication Date: 2024.08.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12074063B2 patent drawing
  • US12074063B2 patent drawing
  • US12074063B2 patent drawing

AI summary

A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.