Contactless Nonvolatile Memory Array With Shared Extremity Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile memory cell arrays face challenges in reducing cell size and minimizing failure causes such as shorting between structures, particularly due to the presence of electrical contacts.
Innovation Solution
A contactless array of nonvolatile memory cells is designed with a substantially single crystalline semiconductor substrate, featuring a unique arrangement of floating gates, control gates, erase gates, and word lines, where cell units share common gates and regions, and electrical contacts are made only at the extremities, eliminating the need for individual plugs and reducing the risk of shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory cell arrays with individual electrical contacts are used, then data storage and retrieval capabilities are maintained, but cell size increases and failure risk increases due to shorting between contacts
Solution Approach 1:
The patent removes individual electrical contacts from each memory cell and extracts only the essential function of electrical connection by implementing shared contacts at array extremities. This eliminates the harmful shorting between contacts while maintaining data storage and retrieval capabilities through the contactless array architecture.
Solution Approach 2:
The patent merges multiple individual contact functions into shared contacts located at array extremities. By combining the electrical connection function across multiple cells through common gates and shared contacts, the design reduces the total number of contacts and eliminates shorting risks between individual cell contacts.
2Quantity of substance
If individual electrical contacts are provided for each memory cell, then data storage capability is maintained, but cell size increases
Solution Approach 1:
The patent merges multiple individual contact structures into shared contacts at array extremities. By combining the electrical connection function across multiple cells through common gates and shared contacts, the design reduces the total area occupied by contacts and interconnections, thereby reducing overall cell size while maintaining data storage capacity.
Solution Approach 2:
The shared contacts and common gates serve multiple functions across multiple memory cells simultaneously. This multi-functionality allows the same structural elements to be shared by multiple cells, reducing the area required per cell while maintaining full data storage capability.
3Reliability
If electrical contacts are eliminated from memory cells, then cell size is reduced and failure risk is minimized, but data storage and retrieval capabilities must be maintained through alternative structures
Solution Approach 1:
The patent segments the array into units with shared contacts at extremities and implements contactless structures within each unit. By dividing the array into manageable segments with shared resources, the design eliminates individual contacts while maintaining data storage and retrieval through the segmented contactless architecture.
Solution Approach 2:
The patent introduces common gates and shared contacts as intermediary structures that mediate between the eliminated individual contacts and the floating gates. These intermediaries enable data storage and retrieval functions to be maintained without direct electrical contacts to each memory cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a smaller cell size and reduces failure causes by eliminating electrical contacts, thereby enhancing the reliability and efficiency of memory cell operations while maintaining effective data storage and retrieval capabilities.
Implementation Method 1
A first control gate is over the first floating gate and is capacitively coupled thereto. A second control gate is over the second floating gate and is capacitively coupled thereto.
Implementation Method 2
Application of a voltage to the first erase gate produces a first junction in the first area of the substrate. Application of a voltage to the second erase gate produces a second junction in the second area of the substrate.
Data Source
AI summary
A plurality of non-volatile memory cell units are arranged in rows and columns in a single crystalline semiconductor substrate of a first conductivity type. Each cell unit has a first region of a second conductivity type in the substrate along the planar surface, and a second region of the second conductivity, spaced apart from the first region, with a channel region therebetween. The channel region has a first portion adjacent to the first region, a third portion adjacent to the second region and a second portion therebetween. A first and second floating gates are over the first portion and third portion respectively and are insulated therefrom. A first and second control gates are over the first and second floating gates respectively and are capacitively coupled thereto. A first and second erase gates are over the first and second regions respectively and are insulated therefrom. A word line is over the second portion and is insulated therefrom. Electrical contacts to the array are made along the extremities of the array.