Contactor Control Circuit With Delay Hold Against False Battery Trips

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Solution Overview

Problem

Temporary communication failures between the microcontrol unit (MCU) and power management integrated circuit (PMIC) in battery packs can lead to false alarms, causing unnecessary protection operations due to electrical shocks or physical impacts, which should be avoided.

Innovation Solution

A contactor control circuit with a retention function that includes a first inverting circuit, a delay circuit, a D-flip-flop, and a logical sum circuit to generate a control signal, ensuring the contactor maintains its state for a predetermined period even if an abnormal signal is output, preventing immediate disconnection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the contactor control circuit immediately responds to an abnormal signal by disconnecting the contactor, then the battery protection response speed is improved, but false protection operations occur due to temporary communication failures

Engineering Contradiction:
Improveprotection response speedVSAvoidprotection operation accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The delay circuit performs preliminary action by introducing a predetermined time delay before the contactor disconnects. When an abnormal signal is detected, the delay circuit holds the contactor in its current state for a preset period (e.g., 100ms) before executing disconnection. This preliminary delay allows temporary communication failures to self-correct, preventing false protection operations while maintaining rapid response to genuine abnormalities.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the contactor control circuit uses a simple abnormal signal detection mechanism, then the device complexity is reduced, but false alarms occur due to temporary communication failures

Engineering Contradiction:
Improvecontrol circuit complexityVSAvoidcommunication failure tolerance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The delay circuit acts as an intermediary between the abnormal signal detection and the contactor control. Instead of directly responding to abnormal signals, the control circuit routes signals through the delay circuit which filters out temporary communication failures. This intermediary mechanism adds minimal complexity while significantly improving reliability by distinguishing between transient and persistent abnormalities.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the contactor maintains its state for a predetermined period after abnormal signal detection, then false protection operations are prevented, but the protection response time is extended

Engineering Contradiction:
Improveprotection operation accuracyVSAvoidprotection response time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The delay circuit uses parameter changes (specifically time duration) to resolve the contradiction. By adjusting the predetermined delay period to an optimal value (e.g., 100ms), the system balances between preventing false operations and maintaining timely protection. This parameter optimization ensures the delay is sufficient to filter temporary failures but short enough to provide rapid protection when needed.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4641878A1Contactor control circuit and battery pack including the same
Publication Date: 2025.10.29 SAMSUNG SDI CO LTD
  • EP4641878A1 patent drawingFigure 1
  • EP4641878A1 patent drawingFigure 2
  • EP4641878A1 patent drawingFigure 3

AI summary

A contactor control circuit according to embodiments of the present disclosure includes a first inverting circuit that generates an inverted drive signal by inverting a drive signal received through a first input terminal, a second inverting circuit that generates an inverted abnormal signal by inverting the abnormal signal received through the second input terminal, a delay circuit that outputs a high-level reset signal for a preset delay time if the inverted abnormal signal transitions from low level to high level, a D-flip-flop that generates an output signal based on the driving signal, the inverted driving signal, the inverted abnormal signal, and the reset signal, and a logical sum circuit that generates a control signal by performing a logical sum operation on the driving signal and the output signal.