Contactor Control Circuit With Delay Hold Against False Faults
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Solution Overview
Problem
Temporary communication failures between the microcontrol unit (MCU) and power management integrated circuit (PMIC) in battery packs can lead to false error signals, causing unnecessary protection operations.
Innovation Solution
A contactor control circuit with a retention function that includes a first inverting circuit, a delay circuit, a D-flip-flop, and a logical sum circuit to process driving and abnormal signals, ensuring the contactor maintains its state for a predetermined period even in the presence of temporary abnormal signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the contactor control circuit uses simple direct control, then device complexity is reduced, but inability to distinguish temporary failures from real errors occurs
Solution Approach 1:
The delay circuit performs preliminary time-based filtering of abnormal signals before they reach the control logic. By introducing a predetermined delay, temporary communication failures that self-correct within the delay period are filtered out, while genuine faults persist and trigger protection, thereby improving error detection accuracy without requiring complex diagnostic algorithms
Solution Approach 2:
The patent uses simple, inexpensive components (delay circuit with resistors and capacitors, flip-flop) to achieve sophisticated error filtering functionality. Rather than using complex microcontroller-based diagnostic routines, the patent employs passive electronic components that provide temporary signal holding and filtering, achieving reliable error distinction with minimal added complexity
Data Source
AI summary
A contactor control circuit according to embodiments of the present disclosure includes a first inverting circuit that generates an inverted drive signal by inverting a drive signal received through a first input terminal, a second inverting circuit that generates an inverted abnormal signal by inverting the abnormal signal received through the second input terminal, a delay circuit that outputs a high-level reset signal for a preset delay time if the inverted abnormal signal transitions from low level to high level, a D-flip-flop that generates an output signal based on the driving signal, the inverted driving signal, the inverted abnormal signal, and the reset signal, and a logical sum circuit that generates a control signal by performing a logical sum operation on the driving signal and the output signal.