Container Packet Bridging With DPU Offload for Low-Latency Routing

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Solution Overview

Problem

Traditional packet processing systems face inefficiencies due to the use of proprietary TCAMs requiring reordering of routes and high CPU load, leading to increased latency and reduced throughput.

Innovation Solution

Implementing a DPU-based offload architecture that utilizes CAM with exact match flow entries and vector packet processing (VPP) to minimize latency and offload packet processing from CPUs, allowing for just-in-time programming and automated removal of entries without reordering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If proprietary TCAMs are used for route programming, then routing functionality is achieved, but reordering of routes is required and device complexity increases

Engineering Contradiction:
Improveroute programming simplicityVSAvoidTCAM structure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent extracts the route reordering requirement from the TCAM structure by implementing a bridge that separates the hardware forwarding plane (which requires exact match and cannot reorder) from the control plane (which handles route installation and reordering). This allows the hardware to use simple CAM tables without reordering capabilities while the software bridge handles the complex route management.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The software bridge acts as an intermediary between the control plane and the hardware forwarding plane. It receives routes from the control plane, programs them into the hardware CAM tables in the correct order, and manages the installation timing to ensure proper forwarding behavior without requiring the hardware TCAM itself to perform reordering operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If traditional packet processing is performed on CPUs, then packet handling is achieved, but CPU load increases and throughput decreases

Engineering Contradiction:
Improvepacket processing throughputVSAvoidCPU processing load
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts packet processing functionality from the CPU by implementing a dedicated software bridge that handles packet forwarding decisions. This bridge offloads the majority of packet processing from the CPU, allowing the CPU to focus on control plane functions while the bridge handles data plane forwarding, thereby increasing throughput and reducing CPU load.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The software bridge serves as an intermediary between the network interfaces and the CPU. It intercepts packets, makes forwarding decisions based on programmed routes, and directs traffic without requiring CPU intervention for each packet, thus significantly reducing CPU processing load and improving overall system throughput.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If exact match flow entries are programmed into hardware switch pipeline, then latency is reduced, but the system requires just-in-time programming capability

Engineering Contradiction:
Improvepacket processing latencyVSAvoidprogramming control complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The software bridge performs preliminary actions by pre-programming exact match flow entries into the hardware switch pipeline before packets arrive. This allows the hardware to immediately forward packets using the pre-configured routes without requiring complex runtime decision-making, thereby reducing latency while the bridge manages the programming timing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the software bridge monitors packet flows and dynamically programs exact match entries into the hardware pipeline based on observed traffic patterns. This feedback loop allows the system to optimize latency by programming routes just-in-time based on actual traffic needs while maintaining manageable programming complexity through automated monitoring and adjustment.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20260023705A1Packet processing for clustered containers using internal bridging and an offload architecture
Publication Date: 2026.01.22 DELL PROD LP
  • US20260023705A1 patent drawing
  • US20260023705A1 patent drawing
  • US20260023705A1 patent drawing

AI summary

A method for processing packets. The method comprising selecting, by an application executing on a container in a pod on a physical host, a transmission interface from a set of transmission interfaces over which to transmit a packet, where the set of transmission interfaces comprises a virtual Ethernet interface and a virtual function, where the set of transmission interfaces are associated with the pod, and where the transmission interface is the virtual Ethernet interface. The method further comprises receiving the packet by a host bridge in the physical host, wherein the packet is destined for a second container on a second pod in executing on the physical host, and transmitting, by the host bridge, the packet to a second virtual Ethernet interface, wherein the second pod is associated with the second virtual Ethernet interface.