Container-Shaped Memory Electrode for Higher Capacitance
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Solution Overview
Problem
Conventional etching techniques for high-aspect-ratio capacitors in memory devices result in reduced capacitance due to smaller dimensions at the bottom of the recess, leading to poor device performance and material loss, and wet etch techniques cause device defects.
Innovation Solution
A memory device design featuring a container-shaped bottom electrode with a dielectric structure and top electrode structure, where the dielectric portions cover the top corners of a support layer, increasing the overall thickness and preventing leakage current, and a method involving sequential layer formation and dry etching to enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used for high-aspect-ratio capacitors, then the capacitor structure can be formed, but the dimension at the bottom of the recess becomes smaller, reducing capacitance
Solution Approach 1:
Instead of forming a traditional tapered recess that narrows at the bottom, the patent inverts the approach by creating a container-shaped electrode where the bottom opening is wider than the top opening. This is achieved through selective etching processes that remove material in reverse sequence, allowing the capacitor to maintain larger dimensions at the bottom where capacitance is most critical, while still achieving high aspect ratio.
Solution Approach 2:
The patent transitions from a simple recess geometry to a three-dimensional container structure with vertical walls and a flat bottom. By adding the dimensional aspect of vertical sidewalls that extend upward from a wide bottom opening, the design maintains large bottom area for capacitance while achieving high aspect ratio through the vertical dimension, rather than relying on tapered narrowing.
2Ease of manufacture
If conventional wet etch techniques are used, then etching can be performed, but significant material loss and device defects occur due to poor control
Solution Approach 1:
The patent replaces conventional wet chemical etching with a dry plasma-based etching process. This substitution uses physical plasma reactions and ion bombardment instead of liquid chemicals, providing superior control over the etching front, reduced material loss, fewer device defects, and better ability to form the precise container-shaped electrode geometry with vertical sidewalls.
3Reliability
If the dielectric structure thickness is increased to prevent leakage current, then leakage prevention improves, but device complexity increases
Solution Approach 1:
The patent applies a liner dielectric layer conformally over the container-shaped electrode before forming the main dielectric structure. This preliminary action creates a protective barrier that prevents leakage current at the critical electrode-dielectric interface, while the conformal application ensures uniform coverage without adding excessive complexity. The liner is deposited in advance to seal potential defect sites before subsequent processing steps.
Solution Approach 2:
The patent implements different dielectric layers with different properties at different locations: a liner dielectric layer conformally covering the electrode surface for leakage prevention, and a bulk dielectric material filling the remaining space. This local differentiation addresses leakage at the critical interface while maintaining overall structural efficiency, rather than uniformly increasing dielectric thickness throughout.
Data Source
AI summary
The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.