Container-Shaped Vertical 2D-Material Transistors for Memory Arrays
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Solution Overview
Problem
Current methods face challenges in incorporating two-dimensional-materials into transistors, particularly in developing improved transistor configurations that leverage their large band gap and good mobility properties.
Innovation Solution
The method involves forming vertical transistors with two-dimensional-materials as the active channel material, where the two-dimensional-material is integrated into trenches within the transistor structure, directly contacting the conductive structures, and patterned into segments with upwardly-opening container-shaped structures, enabling short channel lengths and effective electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-dimensional-materials are incorporated into transistors, then mobility properties and band gap are improved, but manufacturing difficulty increases
Solution Approach 1:
The two-dimensional material is segmented into discrete channel regions between source and drain contacts, allowing selective placement and integration into existing transistor architectures. This segmentation enables controlled incorporation while maintaining manufacturing feasibility through standardized processing steps.
Solution Approach 2:
Dielectric materials and insulating layers are introduced as intermediary elements between the two-dimensional material and surrounding structures. These intermediaries facilitate integration by providing electrical isolation, mechanical support, and process compatibility, thereby reducing manufacturing difficulty while preserving the superior electrical properties of the two-dimensional channel material.
2Length of moving object
If vertical FET configuration is used, then channel length is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The transistor channel is configured vertically rather than laterally, transitioning from a planar two-dimensional layout to a three-dimensional vertical structure. This dimensional change enables short channel lengths to be achieved through vertical stacking, where precision requirements are distributed across multiple fabrication layers rather than demanding extreme lateral alignment precision.
Solution Approach 2:
The vertical FET structure employs nested configurations where gate regions, channel regions, and contact structures are stacked vertically in defined sequences. This nesting approach allows short channel dimensions to be realized through vertical integration of multiple components, reducing the lateral precision requirements while maintaining manufacturing feasibility through sequential processing steps.
Data Source
AI summary
Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.