Contention Blocking Buffer for Multiprocessor Memory Access

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Solution Overview

Problem

In multiprocessor devices, memory contention occurs when multiple processor cores attempt to access the same shared memory location concurrently, leading to delayed execution and reduced processing efficiency due to the need for synchronization operations like locking and unlocking semaphores.

Innovation Solution

Implementing a contention blocking buffer that stores memory addresses of shared memory locations, delaying probes seeking ownership until the processor core has completed operations, thereby preventing premature ownership transfer and allowing time for semaphore locking operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If processor cores implement synchronization schemes with lock operations to access shared memory locations, then memory access correctness is improved, but processing efficiency deteriorates due to instruction delays

Engineering Contradiction:
Improvememory access correctnessVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The home agent performs preliminary actions by sending probe messages to other processor cores before granting ownership of a shared memory location. This preliminary probing ensures that no other core is currently accessing the memory location, preventing future conflicts and reducing the need for repeated lock operations and delays.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The home agent acts as an intermediary between processor cores competing for shared memory access. It mediates the ownership transfer by receiving probe messages, checking current ownership status, and coordinating the transfer of ownership to the requesting core. This intermediary role streamlines the synchronization process and reduces direct contention between cores.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple processor cores attempt to lock shared memory region concurrently, then memory access flexibility is improved, but execution speed deteriorates due to instruction delays

Engineering Contradiction:
Improvememory access flexibilityVSAvoidexecution speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The system implements feedback through probe messages that provide real-time information about current memory location ownership to the home agent. When a processor core wants to access a shared memory location, it sends a probe message that gives feedback on whether the location is currently owned by another core, enabling informed decisions about access timing and reducing unnecessary delays.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Processor cores autonomously determine whether to proceed with memory access operations based on probe message responses. Instead of being passively blocked by traditional locking mechanisms, cores can self-service by checking ownership status through probes and deciding whether to wait or proceed, thereby maintaining flexibility while improving execution speed.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9892063B2Contention blocking buffer
Publication Date: 2018.02.13 ADVANCED MICRO DEVICES INC
  • US9892063B2 patent drawing
  • US9892063B2 patent drawing
  • US9892063B2 patent drawing

AI summary

In response to a processor receiving data associated with a shared memory location, a contention blocking buffer stores a memory address of the shared memory location. In response to a probe seeking to take ownership of the shared memory location, the contention blocking buffer determines if the memory address indicated by the probe is stored at the contention blocking buffer. If so, the contention blocking buffer blocks the probe, thereby preventing another processor from taking ownership of the shared memory location.