Context-aware Data Cache Memory for Side Channel Attack Mitigation
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Solution Overview
Problem
Side channel attacks exploit microarchitectural speculation in CPUs to breach architectural security protections, specifically through speculative execution, allowing attackers to infer sensitive information by manipulating cache states and timing differences.
Innovation Solution
Incorporating a translation context (TC) into the data cache memory to differentiate between allocation and access contexts, ensuring that cache entries are only accessed by the same translation context that allocated them, thereby preventing attackers from exploiting cache timing signals to reveal secret information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a globally shared inclusive last level cache (LLC) is used to improve processor performance, then cache hit rate increases, but side channel attacks become more effective
Solution Approach 1:
The patent segments the shared LLC into context-specific cache spaces by introducing a cache space identifier (CSID) that is associated with each cache line. This segmentation allows different translation contexts (e.g., virtual machines, privilege modes) to have isolated cache views, preventing side channel attacks while maintaining the performance benefits of the shared cache infrastructure.
Solution Approach 2:
The patent introduces a cache space identifier (CSID) as an intermediary mechanism between the cache control logic and cache lines. The CSID acts as a mediator that determines which translation contexts can access which cache lines, thereby preventing unauthorized access while allowing legitimate performance optimization.
2Adaptability or versatility
If cache entries are shared across different translation contexts to improve resource utilization, then cache efficiency increases, but information leakage through timing signals increases
Solution Approach 1:
The patent applies local quality by making cache access permissions context-specific. Each cache line is tagged with a CSID that determines which translation contexts can access it. This allows the cache to be shared among multiple contexts when safe, while preventing information leakage by blocking access when contexts differ.
Solution Approach 2:
The patent changes the cache access parameter from a simple hit/miss determination to a context-aware access control mechanism. The cache control logic now evaluates both the address and the translation context (via CSID) to determine cache behavior, thereby preventing timing-based information leakage while maintaining efficient resource utilization.
3Productivity
If speculative execution is enabled to improve processor throughput, then instruction execution speed increases, but microarchitectural traces of privileged information are created
Solution Approach 1:
The patent applies preliminary anti-action by proactively preventing speculative execution that would create exploitable traces. The cache control logic monitors translation context changes and blocks speculative cache accesses when the context differs from the original allocation context, thereby preventing the creation of microarchitectural traces before they can be exploited.
Data Source
AI summary
A data cache memory mitigates side channel attacks in a processor that comprises the data cache memory and that includes a translation context (TC). A first input receives a virtual memory address. A second input receives the TC. Control logic, with each allocation of an entry of the data cache memory, uses the received virtual memory address and the received TC to perform the allocation of the entry. The control logic also, with each access of the data cache memory, uses the received virtual memory address and the received TC in a correct determination of whether the access hits in the data cache memory. The TC includes a virtual machine identifier (VMID), or a privilege mode (PM) or a translation regime (TR), or both the VMID and the PM or the TR.