Context-Aware Cryptographic Computing for Transient Side-Channel Security

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Solution Overview

Problem

Existing cryptographic computing systems face challenges in proactively blocking out-of-bound memory accesses and ensuring cryptographic isolation of memory regions, leading to potential data corruption and integrity issues, as existing solutions often require additional storage and performance overhead.

Innovation Solution

Implement cryptographic isolation within the processor core by encoding memory addresses with metadata and using secret keys and tweaks to enforce memory access controls, allowing encryption and decryption operations to be performed inline, thereby preventing unauthorized access and ensuring data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cryptographic isolation is implemented using external memory controllers, then data security is improved, but performance overhead and device complexity increase

Engineering Contradiction:
Improvedata securityVSAvoidperformance overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges cryptographic isolation functionality directly into the processor core by integrating encoded pointer validation logic with the memory management unit. This consolidation eliminates the need for separate external memory controllers to perform security checks, thereby reducing performance overhead while maintaining data security. The encoded pointer mechanism is tightly coupled with memory access operations within the core, enabling inline security verification without external intervention.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If additional storage mechanisms are added for cryptographic isolation, then data integrity is improved, but device complexity and storage overhead increase

Engineering Contradiction:
Improvedata integrityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the existing pointer structure universal by adding encoded metadata fields that serve multiple functions: memory address identification, access permission validation, and cryptographic isolation enforcement. This multi-functional encoding approach eliminates the need for separate storage mechanisms dedicated solely to security metadata, thereby reducing device complexity while ensuring data integrity through comprehensive pointer validation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If inline encryption and decryption operations are performed within the processor core, then cryptographic isolation is improved, but processing overhead increases

Engineering Contradiction:
Improvecryptographic isolationVSAvoidprocessing overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary encoding of pointers with cryptographic metadata before memory access operations occur. By pre-encoding the pointers with isolation context information and validation tags, the system enables fast inline verification during memory access without requiring complex real-time encryption/decryption operations. This preliminary action reduces processing overhead while maintaining strong cryptographic isolation through pre-computed security credentials.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12481502B2Cryptographic computing with context information for transient side channel security
Publication Date: 2025.11.25 INTEL CORP
  • US12481502B2 patent drawing
  • US12481502B2 patent drawing
  • US12481502B2 patent drawing

AI summary

In one embodiment, a processor includes a memory hierarchy that stores encrypted data, tracking circuitry that tracks an execution context for instructions executed by the processor, and cryptographic computing circuitry to encrypt/decrypt data that is stored in the memory hierarchy. The cryptographic computing circuitry obtains context information from the tracking circuitry for a load instruction to be executed by the processor, where the context information indicates information about branch predictions made by a branch prediction unit of the processor, and decrypts the encrypted data using a key and the context information as a tweak input to the decryption.