Context Cache Lookup for Faster I/O Address Remapping
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Solution Overview
Problem
The challenge of improving the performance of address remapping and cache searching speed in I/O devices within virtualized computing environments has become critical with the increase in computing power, as existing methods struggle to efficiently deliver data to the CPU in time.
Innovation Solution
A method and device for rapidly searching a cache by translating a source identifier (SID) to a domain identifier (DID) using an extended flag to differentiate between normal and extended context entries, and employing a two-step search process involving a context cache and an IOTLB cache, along with parallel processing units to handle remapping requests efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional cache searching methods are used in I/O devices, then the system can maintain simpler hardware structure, but the cache search speed and address remapping performance deteriorate
Solution Approach 1:
The patent segments the cache searching process into two distinct stages: first searching the context cache for context entries, then searching the IOTLB cache for translation entries. This segmentation allows each cache to be optimized for its specific purpose, improving overall search speed without requiring a single complex cache structure
Solution Approach 2:
The patent introduces an intermediary mechanism (the context cache with context entries containing DID information) that mediates between the I/O device and the IOTLB cache. This intermediary enables faster preliminary filtering and directs subsequent searches more efficiently, improving cache hit rates without significantly increasing hardware complexity
2Productivity
If address remapping performance is improved through enhanced cache searching, then data delivery speed to CPU increases, but the system complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-loading context entries into the context cache with essential information (DID, SID, IOTLB base address). This preliminary organization of data enables faster subsequent lookups during address remapping operations, improving productivity without requiring complex runtime processing
Solution Approach 2:
The patent adds a new dimension to the cache hierarchy by introducing the context cache as a separate layer before the traditional IOTLB cache. This dimensional addition creates a two-stage lookup process that improves address remapping performance while maintaining manageable system complexity through clear separation of concerns
3Reliability
If a single cache is used for both context and translation entries, then hardware structure remains simple, but cache hit rate and search efficiency deteriorate
Solution Approach 1:
The patent segments the unified cache into two specialized caches: context cache for storing context entries and IOTLB cache for storing translation entries. This segmentation increases cache hit rates by reducing conflicts and improving locality, while the modular structure keeps overall complexity manageable
Solution Approach 2:
The patent applies local quality by optimizing each cache for its specific function: the context cache is optimized for storing and retrieving context entries with DID information, while the IOTLB cache is optimized for translation lookups. This specialization improves overall system reliability and cache hit rates without requiring a single overly complex unified cache
Data Source
AI summary
A method and a device for rapidly searching a cache are provided. The method for rapidly searching a cache includes: translating a source identifier (SID) to a domain identifier (DID) according to an extended flag from the software by searching a context cache, wherein the extended flag indicates that a current context entry stored in the context cache is a normal context entry or an extended context entry.