Context-Driven Memory Circuits for PLD Resource Optimization
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Solution Overview
Problem
Memory circuits in programmable logic devices (PLDs) face inefficiencies due to increased memory size, access power, and area requirements, particularly with look-up table (LUT) memory and dedicated random access memory blocks (BRAMs), which can limit speed and underutilize capabilities.
Innovation Solution
A memory device with a random access memory (RAM) circuit and a shared routing resource, utilizing a memory partition register circuit to store context partitions and pointer register circuits to provide access through a switching fabric, allowing time-sharing and efficient access across multiple contexts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If LUT memory is configured for dual function as small memory block, then memory versatility is improved, but memory size and access power increase
Solution Approach 1:
The memory block is segmented into multiple context partitions (first context partition, second context partition, etc.) that can be independently accessed. Each partition contains context-specific data, allowing the same physical memory resources to serve multiple functional contexts without increasing total memory size.
Solution Approach 2:
The memory block is designed to serve multiple functions by time-sharing access between different contexts. The same memory infrastructure (storage cells, read/write ports) is universally utilized across multiple context partitions, eliminating the need for separate memory blocks for each context.
2Adaptability or versatility
If LUT memory is configured for dual function as small memory block, then memory versatility is improved, but access power increases
Solution Approach 1:
The memory is divided into context partitions with selective access control. The read/write ports can selectively access only the required context partition, avoiding unnecessary power consumption from accessing entire memory blocks or irrelevant partitions.
Solution Approach 2:
The memory system dynamically switches between different context partitions based on operational requirements. Context selection logic and pointer mechanisms enable flexible, dynamic access to only the active context, reducing access power compared to static dual-function configurations.
3Speed
If BRAM access rate significantly exceeds switching fabric access rate, then memory speed is improved, but switching fabric becomes limiting factor and BRAM capabilities are underutilized
Solution Approach 1:
The BRAM is segmented into multiple context partitions that can be accessed in parallel or sequentially. This segmentation allows the fast BRAM to serve multiple contexts simultaneously, increasing overall utilization and preventing the switching fabric from being the sole limiting factor.
Solution Approach 2:
The memory system maintains continuous useful action by pre-loading and caching data in appropriate context partitions before they are needed by the switching fabric. Pointer mechanisms and context management logic ensure that the BRAM is continuously utilized at full speed, eliminating idle cycles.
4Area of stationary object
If multiple contexts share memory through time-sharing, then memory area efficiency is improved, but access complexity increases
Solution Approach 1:
The memory is segmented into clearly defined context partitions with dedicated address ranges. This segmentation simplifies access control logic, as each context has its own address space that can be independently managed without complex arbitration.
Solution Approach 2:
Context management logic and pointer registers act as intermediaries between the switching fabric and the partitioned memory. These intermediaries handle the complexity of context switching, partition selection, and address translation, shielding the user from complexity while enabling efficient time-sharing access.
Data Source
AI summary
A memory device can be used with a shared routing resource that provides access to the memory device. The memory device can include a random access memory (RAM) circuit that includes a plurality of ports configured to provide access to the RAM circuit by the shared routing resource. A memory partition register circuit can be configured to store a plurality of addresses specifying respective context partitions within the RAM circuit. A plurality of pointer register circuits that can each be associated with a corresponding port of the plurality of ports and can be configured to store a respective set of pointers that specify a location in the RAM circuit relative to a respective context partition. Addressing logic that can be configured to provide access to the RAM circuit using the respective set of pointers for each port.