Context-Based Protection System Bus Latency
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Solution Overview
Problem
Embedded systems face challenges in ensuring security, functional safety, and performance due to the need to protect secure memory and MMIO address regions from unauthorized accesses, while also preventing bus interference, which can lead to latency issues.
Innovation Solution
A context-based protection system is implemented using a configurable bus architecture with memory protection units (MPUs), shared memory protection units (SMPUs), and peripheral protection units (PPUs) to differentiate between secure and non-secure accesses and manage protection contexts, allowing for secure and efficient data transfer while minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If protection structures (MPUs, SMPUs, PPUs) are implemented to restrict unauthorized access to secure memory and MMIO address regions, then security is improved, but bus latency increases due to additional access control checks
Solution Approach 1:
The protection structures are configured with access control rules in advance before actual data transfers occur. The MPUs, SMPUs, and PPUs are pre-programmed with permission matrices and protection attributes that automatically evaluate access requests without requiring runtime security decisions, thereby reducing bus latency while maintaining security
Solution Approach 2:
The patent introduces protection structures (MPUs, SMPUs, PPUs) as intermediary components between the bus master and the protected resources. These intermediaries automatically evaluate access requests against pre-configured rules, isolating the security evaluation logic from the main data path and minimizing the impact on bus performance
2Productivity
If multiple protection structures operate within a unified memory architecture to maintain system performance, then productivity is improved, but device complexity increases
Solution Approach 1:
The protection system is segmented into three distinct functional units: Memory Protection Units (MPUs) for memory regions, Shared Memory Protection Units (SMPUs) for shared memory, and Peripheral Protection Units (PPUs) for peripheral devices. Each unit operates independently with specialized logic, allowing parallel evaluation of access requests to different resource types, thereby maintaining system performance while managing complexity through functional decomposition
Solution Approach 2:
The protection structures are designed with universal interfaces and common evaluation logic that can handle multiple types of access requests (read, write, execute, device access) through a unified permission matrix mechanism. This multi-functionality allows the same architectural pattern to protect diverse resources without proportionally increasing complexity
Data Source
AI summary
A context-based protection system uses tiered protection structures including master protection units, shared memory protection units, a peripheral protection units to provide security to bus transfer operations between central processing units (CPUs), memory array or portions of arrays, and peripherals.