Context-Sensitive Barrier Execution for Multi-Context Data Processing

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Solution Overview

Problem

Data processing apparatuses face challenges in efficiently managing access ordering constraints across multiple contexts, particularly in real-time contexts where delays are critical, due to the need to wait for accesses initiated in non-real-time contexts with longer latencies.

Innovation Solution

The data processing apparatus selectively enforces access ordering constraints only for accesses initiated in the current context, using a store buffer to tag and manage pending accesses with context identifiers, allowing for flexible enforcement of constraints based on context, thereby reducing the impact of multiple contexts on real-time operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the data processing apparatus enforces access ordering constraints for all contexts, then memory coherence is maintained, but real-time context performance deteriorates due to delays from non-real-time accesses

Engineering Contradiction:
Improvememory coherenceVSAvoidreal-time context performance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the access ordering constraint enforcement by context type. The memory management unit applies different enforcement rules based on whether the access originates from a real-time context or a non-real-time context. This segmentation allows the system to maintain memory coherence for non-real-time contexts while exempting real-time contexts from the same constraints, thereby resolving the contradiction between reliability and speed.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the data processing apparatus waits for all preceding accesses to complete before executing subsequent instructions, then access ordering is enforced, but processing productivity decreases

Engineering Contradiction:
Improveaccess orderingVSAvoidprocessing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by making the access ordering enforcement selective rather than universal. The memory management unit examines the context of each access and applies ordering constraints only where necessary (non-real-time contexts) while allowing out-of-order execution in real-time contexts. This localized application of quality control maintains reliability where needed while maximizing productivity overall.

Inventive Principle:
Principle #3Local quality

3Reliability

If the data processing apparatus enforces strict access ordering across multiple contexts, then memory coherence is ensured, but device complexity increases

Engineering Contradiction:
Improvememory coherenceVSAvoidcontext management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces dynamic behavior to the access ordering enforcement mechanism. The memory management unit dynamically determines whether to enforce ordering constraints based on the current context's real-time status. This dynamic adaptation allows the system to simplify operations for real-time contexts while maintaining coherence for non-real-time contexts, thereby managing device complexity effectively without sacrificing reliability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3218796B1Context sensitive barrier instruction execution
Publication Date: 2020.05.06 ARM LTD
  • EP3218796B1 patent drawingFigure 1~2
  • EP3218796B1 patent drawingFigure 3A~3B
  • EP3218796B1 patent drawingFigure 4

AI summary

Apparatus for data processing and a method of data processing are provided, according to which the processing circuitry of the apparatus can access a memory system and execute data processing instructions in one context of multiple contexts which it supports. When the processing circuitry executes a barrier instruction, the resulting access ordering constraint may be limited to being enforced for accesses which have been initiated by the processing circuitry when operating in an identified context, which may for example be the context in which the barrier instruction has been executed. This provides a separation between the operation of the processing circuitry in its multiple possible contexts and in particular avoids delays in the completion of the access ordering constraint, for example relating to accesses to high latency regions of memory, from affecting the timing sensitivities of other contexts.