Context-Sensitive Rule-Set for IC Design Convergence
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Solution Overview
Problem
Current hierarchical design flows for integrated circuits (ICs) face challenges in convergence due to hidden assumptions and communication gaps between geographically distributed design teams, leading to potential non-convergence and delays in achieving a functional IC design.
Innovation Solution
A progressive hierarchical design rule (HDR) approach with a context-sensitive rule-set is employed, using EDA tools to create, verify, and modify functional, logical, and physical circuits, ensuring compliance across various design stages to prevent mistakes from moving downstream and promote convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hierarchical design flows are used with geographically distributed design teams, then design flexibility and innovation are improved, but communication gaps and hidden assumptions lead to design non-convergence
Solution Approach 1:
The patent implements continuous verification and validation processes that provide feedback loops throughout the design flow. EDA tools automatically check design compliance at multiple stages, and discrepancies are communicated back to design teams for correction, ensuring convergence while maintaining distributed design flexibility.
Solution Approach 2:
The patent introduces standardized interface specifications and protocol definitions as intermediaries between different design teams and tools. These intermediaries serve as common language and validation criteria that enable seamless integration of independently designed modules while maintaining overall design convergence.
2Reliability
If comprehensive verification is performed at each design stage, then design quality and convergence are improved, but design time and complexity increase
Solution Approach 1:
The patent performs preliminary verification and validation activities early in the design process, before designs are finalized and integrated. By checking compliance with interface specifications and design rules at the conceptual and architectural stages, the system prevents errors from propagating, reducing the need for time-consuming corrections later.
Solution Approach 2:
The patent divides the verification process into discrete, manageable stages corresponding to different design levels (architectural, logical, physical). Each stage verifies specific aspects of the design using specialized EDA tools, allowing parallel execution of verification tasks and reducing overall verification time while maintaining comprehensive quality checking.
Data Source
AI summary
Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.