Context Switch Mechanism for Latch-Based Register Files

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Solution Overview

Problem

The complexity and cost associated with testing integrated circuits, particularly in multi-threaded processing systems, are increased by the need for additional logic and multiplexers to support normal, shadow, and test contexts, leading to undesirable delays in access times.

Innovation Solution

A context switch mechanism that uses a feedback connection between normal and shadow data contexts, eliminating the need for an output multiplexer by shifting data between latch elements in two clock phases, allowing for efficient switching between execution contexts without additional multiplexers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional multiplexers and logic are added to support normal, shadow and test contexts, then context switching capability is improved, but device complexity and access time increase

Engineering Contradiction:

Improvecontext switching capabilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the test context selection functionality into the existing dual-port latch structure by utilizing the shadow port. The same latch elements and interconnect structures serve both normal dual-context switching and test pattern scanning, eliminating the need for separate test multiplexers and reducing overall device complexity while maintaining full context switching capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shadow port of the dual-port latches is made universal by allowing it to serve both as a shadow context storage port during normal operation and as a test pattern input port during test mode. This multi-functionality eliminates dedicated test logic while preserving normal context switching operations through selective activation based on mode control signals

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If additional multiplexers and logic are added to support normal, shadow and test contexts, then context switching capability is improved, but access time increases

Engineering Contradiction:

Improvecontext switching capabilityVSAvoidaccess time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent extracts the test pattern input functionality from the critical data path by routing test patterns through the shadow port rather than requiring them to pass through additional test multiplexers in the main data path. This extraction eliminates the time penalty of extra multiplexing stages while still enabling comprehensive test coverage through the same latch structure

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Test patterns are loaded into the shadow latch elements in advance during a dedicated test phase before being scanned through the latch chain. This preliminary loading separates the test pattern input operation from the critical data access path, ensuring that normal read/write operations maintain their original access times without being affected by test logic

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If dual-port memory cells are used for SRAM-based register files to support normal and shadow contexts, then context switching is enabled, but area and complexity increase

Engineering Contradiction:

Improvecontext switching capabilityVSAvoidlayout area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges test pattern input functionality with the shadow port of existing dual-port latches, eliminating the need for separate test input structures. The same latch elements, interconnect wires, and control logic serve both shadow context storage and test pattern scanning functions, reducing layout area while maintaining full functionality for both normal operation and test modes

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7979684B2Method and context switch device for implementing design-for-testability functionality of latch-based register files

Publication Date: 2011.07.12 QUALCOMM INC

AI summary

A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output.