Configuration Context Switcher With Clocked Re-Timing Storage

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Solution Overview

Problem

Configurable integrated circuits face complexity in efficiently retrieving, decoding, and synchronizing configuration data, leading to increased circuit complexity and power consumption, with existing solutions offering minimal performance gains in configuration setup time or resource usage.

Innovation Solution

The integration of a context switcher with clocked storage circuits and latches that re-time and synchronize configuration data, allowing for efficient switching between different configuration data sets and reducing the need for additional circuitry, while encoding configuration data to minimize storage requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If dual ported RAM is used to provide configuration data at odd and even cycles through separate ports, then configuration data can be alternatively switched between cycles, but circuit complexity increases due to additional multiplexers and control circuitry

Engineering Contradiction:
Improveconfiguration data switching capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The configuration data path is segmented into separate odd-cycle and even-cycle data paths, each with its own storage element. This allows independent control and simplification of each path while maintaining the overall dual-port functionality, reducing the complexity of control multiplexers

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit uses dynamic clocking where storage elements are enabled only during their respective cycles (odd or even) through clock signals. This dynamic activation eliminates the need for complex static multiplexing control circuitry, as each storage element naturally activates only when needed

Inventive Principle:
Principle #15Dynamics

2Reliability

If sense amplifiers and latches are added to capture and stabilize read data from dual ported RAM, then data stability is improved, but circuit complexity and power consumption increase

Engineering Contradiction:
Improvedata stabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The storage elements (flip-flops or latches) inherently provide data stabilization and holding functionality without requiring external sense amplifiers. The clocked storage elements naturally capture and hold data during their respective cycles, eliminating the need for additional sense amplifier circuitry

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The data capture, stabilization, and holding functions are merged into the clocked storage elements themselves. The storage elements perform both the latching function and the data stabilization function that would otherwise require separate sense amplifiers and latches, reducing overall circuit complexity

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If RAM cell size is reduced to increase density, then storage capacity is improved, but configuration setup time and performance gain are minimal

Engineering Contradiction:
ImproveRAM densityVSAvoidconfiguration setup time
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

Configuration data for both odd and even cycles is pre-loaded into separate storage elements during idle periods or previous cycles. This preliminary loading ensures that data is ready and stable when needed, eliminating configuration setup time delays while maintaining high density through efficient storage element usage

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8138789B2Configuration context switcher with a clocked storage element
Publication Date: 2012.03.20 ALTERA CORP
  • US8138789B2 patent drawing
  • US8138789B2 patent drawing
  • US8138789B2 patent drawing

AI summary

Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.