Configuration Context Switching With Clocked Storage Retiming
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Solution Overview
Problem
Configurable integrated circuits face complexity in efficiently retrieving, decoding, and synchronizing configuration data, leading to increased circuit complexity and power consumption, with existing solutions offering minimal performance gains in configuration setup time or resource usage.
Innovation Solution
The integration of a context switcher within the integrated circuit that switchably connects to different configuration data storage elements, re-timing and synchronizing the data to enable efficient retrieval and supply of configuration data to configurable circuits, using clocked storage circuits or latches, and employing encoding techniques to reduce storage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual ported RAM is used to provide configuration data at odd and even cycles, then configuration data can be alternatively provided on different ports, but circuit complexity increases due to additional multiplexers and control circuitry
Solution Approach 1:
The patent extracts the configuration data supply function from the dual ported RAM structure itself and implements it using a single ported RAM combined with clocked storage elements (latches or registers). This separation allows the RAM to be simplified while the timing control is handled by the clocked storage elements, thereby reducing overall circuit complexity while maintaining the ability to supply configuration data at different clock cycles.
Solution Approach 2:
The patent introduces clocked storage elements (latches or registers) as intermediary components between the single ported RAM and the configurable logic. These intermediaries buffer and time the configuration data, enabling flexible timing control without requiring a dual ported RAM structure, thus reducing circuit complexity while preserving adaptability.
2Reliability
If sense amplifiers and latches are added to capture and stabilize read data, then data stability is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the data capture and timing control functions into the clocked storage elements that are already part of the configuration data path. The latches or registers serve dual purposes: they stabilize the configuration data read from RAM and simultaneously provide the timing control needed for sequential operation. This consolidation reduces the need for separate sense amplifiers and additional latches, thereby reducing circuit complexity while maintaining data stability.
3Quantity of substance
If RAM cell size is reduced to increase density, then storage capacity is improved, but configuration setup time and performance gain is minimal
Solution Approach 1:
The patent implements a sequential configuration data supply mechanism using clocked storage elements that pre-load and time the release of configuration data. This preliminary action ensures that configuration data is ready and stabilized before being supplied to the configurable logic, enabling faster configuration setup times without requiring larger RAM cells. The systematic timing control allows efficient data retrieval that compensates for reduced cell size.
4Adaptability or versatility
If multiple configuration data sets are stored and retrieved, then reconfigurability is improved, but power consumption increases
Solution Approach 1:
The patent uses clocked storage elements that operate in a periodic manner, enabling the IC to cycle through multiple configuration data sets at different clock cycles. The clocked latches or registers hold configuration data and release it at appropriate times, allowing the same hardware to support multiple configuration modes without requiring additional always-active circuitry. This periodic operation reduces power consumption compared to continuously active dual ported RAM while maintaining full reconfigurability.
Data Source
AI summary
Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.