Contiguous Page Buffer List Entries for RDMA Caching
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Solution Overview
Problem
Conventional page buffer list (PBL) organizations in RDMA-enabled networks require multiple successive lookups for physically contiguous pages, leading to inefficiencies in data transfer and increased CPU cycles due to data copying overhead, especially in high-speed networks.
Innovation Solution
The method involves encoding at least two page buffer list entries (PBLEs) into two contiguous memory locations, utilizing the remainder of a physical address to enable a single lookup that translates multiple successive segments spanning virtual pages, thereby optimizing caching of translated addresses and reducing data transfer overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional page buffer list (PBL) organizations are used in RDMA-enabled networks, then data transfer can be performed with buffer-to-buffer transfers, but multiple successive lookups are required for physically contiguous pages, increasing CPU cycles and data copying overhead
Solution Approach 1:
The patent combines multiple page buffer list entries (PBLEs) into a single unified data structure called a page buffer list (PBL). This merging allows the system to handle multiple physically contiguous pages through a single lookup operation rather than requiring separate lookups for each page, thereby reducing CPU cycles and improving data transfer efficiency in RDMA networks
2Reliability
If multiple successive lookups are performed for physically contiguous pages, then complete address translation is achieved, but data copying overhead increases and network performance decreases
Solution Approach 1:
The patent performs preliminary organization of page buffer list entries into contiguous blocks before actual data transfer operations. By pre-grouping physically contiguous pages into unified PBL structures, the system ensures that address translation can be completed efficiently without requiring multiple successive lookups during active data transfer, thus maintaining both translation completeness and high network performance
Data Source
AI summary
Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.