Contiguous P-Well/N-Well Memory Cell for Up to 50% Area Reduction
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Solution Overview
Problem
Existing non-volatile memory cells, particularly Multi-Time Programmable (MTP) and Few-Time Programmable (FTP) memories, occupy a large area due to the design of the floating gate and control gate regions, which hinders their efficiency and applicability in space-constrained applications.
Innovation Solution
The memory cell design incorporates a single-poly floating gate with a P-well and an adjacent N-well structure, where the P-well is kept at a lower voltage than the N-well, eliminating the need for insulation between them and allowing for reduced dimensions by utilizing the Channel Hot Electron Injection (CHEI) effect for programming and the Fowler-Nordheim effect for erasing, thereby minimizing the overall cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single-poly floating gate structure with adjacent P-well and N-well is used, then the memory cell area is reduced by up to 50%, but the manufacturing precision requirements increase due to the need for precise voltage control and elimination of insulation between wells
Solution Approach 1:
The patent merges the P-well and N-well structures into adjacent contiguous regions without insulation, eliminating the isolating wall that would otherwise be required. This merging of previously separated structures reduces the overall memory cell area while maintaining functional integrity through precise voltage control during manufacturing and operation.
2Length of stationary object
If the P-well and N-well are kept at different voltages without insulation, then the cell dimensions are reduced, but the device complexity increases due to the need for sophisticated voltage control circuitry
Solution Approach 1:
The patent utilizes parameter changes by dynamically controlling the voltage levels of the P-well and N-well during different operational phases (programming, erasing, reading). By changing voltage parameters in a controlled manner, the system achieves reduced cell dimensions while managing the complexity through standardized voltage control sequences.
3Area of stationary object
If the floating gate and control gate regions are optimized for smaller area, then the memory cell occupies less space, but the programming and erasing operations become more challenging
Solution Approach 1:
The patent segments the memory cell into distinct functional regions (P-well, N-well, floating gate, control gate) with clearly defined voltage control schemes. This segmentation allows for optimized area while maintaining ease of programming and erasing operations by applying voltages to specific segments independently, following the CHEI and Fowler-Nordheim effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a significant reduction in memory cell area by up to 50% compared to prior art, enabling efficient operation with reduced circuitry complexity and power consumption, suitable for applications where space is limited.
Implementation Method 1
utilizing the Channel Hot Electron Injection (CHEI) effect for programming
Implementation Method 2
the Fowler-Nordheim effect for erasing
Data Source
AI summary
A non-volatile memory cell includes a first well of a first conductivity type and a second well of a second conductivity type in a body adjacent to each other; a first conduction region, a second conduction region and a third conduction region in the first well, the first, second and third conduction regions being of the second conductivity type; a control gate region, of the first or second conductivity type, in the second well; a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor; and a floating gate region. The floating gate region has a programming portion overlying the first well and a capacitive portion overlying the second well. The floating gate region forms, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element.