Contingent Load Suppression Circuitry for Vector Processing
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Solution Overview
Problem
Data processing systems face inefficiencies in handling contingent loads during vector load instructions, as they may perform unnecessary loads that trigger memory faults or undesired changes in the architectural state, leading to performance penalties and diagnostic issues.
Innovation Solution
Incorporating fault detection and contingent load suppression circuitry to differentiate between fault-generating and fault-free contingent loads, suppressing only those that match predetermined criteria to avoid unnecessary memory access and diagnostic triggers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all contingent loads are performed during vector load instructions, then data availability is improved, but unnecessary memory faults and diagnostic triggers occur
Solution Approach 1:
The patent applies preliminary action by evaluating whether a contingent load is necessary before actually performing the memory access. The circuitry determines in advance if a load element should trigger a load based on predicate values and program flow analysis, preventing unnecessary memory faults before they occur.
Solution Approach 2:
The patent applies local quality by treating different load elements differently based on their specific characteristics. Each element in the vector load instruction is evaluated individually using element-specific predicate values, allowing selective suppression of only those loads that would cause faults while permitting necessary loads to proceed.
2Productivity
If fault detection circuitry is added to differentiate contingent loads, then memory fault penalties are reduced, but device complexity increases
Solution Approach 1:
The patent applies merging by combining the fault detection functionality with the existing vector load instruction execution pipeline. The contingent load suppression circuitry is integrated into the vector processing unit, sharing resources with the load execution logic rather than being a completely separate system, thus reducing overall complexity.
Solution Approach 2:
The patent applies self-service by using the existing predicate register values and program flow information already available in the processor to perform the fault detection. The system uses its own internal state (predicate values, program counter) to determine which loads to suppress, rather than requiring external control signals or additional complex control logic.
3Loss of energy
If contingent loads are suppressed based on predicate values, then unnecessary memory accesses are prevented, but diagnostic capabilities may be reduced
Solution Approach 1:
The patent applies intermediary by introducing a contingent load suppression circuitry that acts as a mediator between the vector load instruction and the memory access. This intermediary component uses predicate values to intelligently decide which loads to permit and which to suppress, optimizing memory access while maintaining diagnostic capability through controlled suppression rather than blanket blocking.
Data Source
Figure 1
Figure 2~3b
Figure 4
AI summary
A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.