Continuous Active Cell Layout for Semiconductor Leakage Reduction
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Solution Overview
Problem
The transition from single diffusion break (SDB) structures to gate tie-down (continuous active) structures in semiconductor devices leads to increased current leakage due to the lack of isolation regions between source/drain regions, posing a challenge in minimizing device leakage.
Innovation Solution
A technique is developed to evaluate and optimize cell layouts in semiconductor structures by identifying edge source/drain regions, determining their electrical configurations, and computing current leakage values for adjacent cells in both initial and alternative layouts, thereby identifying layouts that reduce total current leakage through the use of power, signal, and floating configurations, and applying these layouts to semiconductor manufacturing systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate tie-down structures are used instead of single diffusion break structures, then device area is reduced and manufacturing is simplified, but current leakage between source/drain regions increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of source/drain regions based on their location and electrical configuration. Edge source/drain regions are identified and assigned specific electrical configurations (tied-off, floating, or connected) based on their adjacency relationships and leakage risk, rather than applying a uniform structure across all regions. This localized approach allows the gate tie-down structure to maintain its manufacturing simplicity while reducing leakage at critical edge regions.
Solution Approach 2:
The patent changes electrical parameters by assigning different electrical configurations to different edge source/drain regions. Instead of a single uniform structure, the system varies the electrical state (tied-off to VDD/VSS, floating, or connected to signals) based on the specific leakage risk and functional requirements of each region. This parameter variation enables leakage reduction while maintaining the continuous active structure benefits.
2Object-generated harmful factors
If isolation regions are added between source/drain regions to reduce current leakage, then leakage is reduced, but device area increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts the isolation function from traditional physical isolation regions and implements it through electrical configurations of edge source/drain regions. Instead of adding physical isolation structures between all source/drain regions, the system identifies edge regions and applies specific electrical configurations (tied-off, floating, or connected) to achieve leakage reduction without the area and complexity overhead of universal isolation regions.
Solution Approach 2:
The patent introduces electrical configurations as an intermediary mechanism to achieve isolation effects. Rather than using physical isolation regions, the system uses electrical connections (or lack thereof) to edge source/drain regions as a mediator to control leakage. This intermediary approach provides leakage control without the structural complexity of physical isolation barriers.
3Object-generated harmful factors
If edge source/drain regions are optimized with specific electrical configurations, then current leakage is reduced, but layout complexity and computational requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-defining a set of standard electrical configurations for edge source/drain regions before final layout completion. The system identifies edge regions and assigns appropriate electrical configurations (tied-off, floating, or connected) in advance, based on predetermined rules and leakage risk assessment. This preliminary configuration reduces leakage while maintaining manageable layout complexity through systematic pre-planning.
Solution Approach 2:
The patent manages layout complexity through parameter changes by varying electrical configurations based on identifiable regional characteristics. Instead of complex global optimization, the system changes electrical parameters (connection state, voltage level) for edge regions based on their position and adjacency relationships. This localized parameter variation achieves leakage reduction with controlled complexity through systematic rules.
Data Source
AI summary
A device comprises memory configured to store program instructions, and processing circuitry, coupled to the memory, and configured to execute the program instructions to perform a process to limit current leakage. The processing circuitry is configured to receive an input of an initial layout of a semiconductor structure comprising a plurality of cells, identify a plurality of edge source/drain regions in respective ones of the cells, determine respective electrical configurations for the edge source/drain regions, compute respective values associated with current leakage for adjacent cells in the initial layout and in a plurality of alternative layouts of the semiconductor structure based at least in part on the respective electrical configurations for the edge source/drain regions, and identify at least one alternative layout of the plurality of alternative layouts to the initial layout that results in at least a reduction of total current leakage from the initial layout.