Continuous-Input ADC Feedback Architecture With Fewer Flash Comparators
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Solution Overview
Problem
Existing analog to digital converters (ADCs) face challenges such as Differential Non Linearity (DNL), Integral Non Linearity (INL), harmonic distortion, aliasing, and require a large chip area due to the need for a big antialiasing filter and a large number of comparators in flash ADCs.
Innovation Solution
The proposed solution involves an analog to digital converter apparatus that includes an integrating block with at least one integrating stage coupled to a flash ADC, a feedback path with a digital to analog conversion block, and a control block performing digital integration. This configuration reduces the number of comparators needed in the flash ADC by implementing a compressed conversion characteristic with exponentially spaced thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a flash ADC with high resolution is used, then measurement precision is improved, but device complexity increases due to the large number of comparators required
Solution Approach 1:
The patent segments the ADC functionality into multiple stages: a first ADC stage with fewer comparators performs initial conversion, and a second ADC stage performs additional conversion on the remaining signal. This segmentation allows achieving high overall resolution (16-24 bits) without requiring a single flash ADC with an impractically large number of comparators (2^16 to 2^24 comparators).
Solution Approach 2:
The patent employs dynamic element matching (DEM) where the number of comparators is dynamically adjusted based on the signal characteristics. The first ADC uses N comparators and the second ADC uses M comparators, where N and M are chosen to optimize performance while minimizing total comparator count. This dynamic approach allows the system to achieve high resolution with fewer total comparators than a static flash ADC design.
2Object-affected harmful factors
If an antialiasing filter with large area is integrated, then aliasing is reduced, but area of the chip increases
Solution Approach 1:
The patent implements a feedback mechanism where the output of the first ADC is fed back to the input, and the output of the second ADC is fed back to the first ADC input. This feedback loop allows the system to achieve anti-aliasing performance without requiring a large integrated antialiasing filter, as the feedback correction compensates for aliasing effects in the digital domain.
Solution Approach 2:
The patent introduces an intermediary digital processing stage between the analog input and the final digital output. The first ADC converts the analog signal to digital, then digital processing (including feedback) occurs, and finally the second ADC performs additional conversion. This intermediary digital stage acts as a mediator that reduces the burden on the analog antialiasing filter, allowing for a smaller filter design.
3Measurement precision
If a Sigma Delta ADC with time continuous input is used, then measurement precision is improved, but device complexity increases due to multiple analog integrators and feedback DACs
Solution Approach 1:
The patent replaces the traditional Sigma Delta ADC architecture with a modified flash ADC structure. Instead of using multiple analog integrators and a feedback DAC (mechanical/analog components), the invention uses multiple flash ADC stages with digital feedback. This substitution of analog mechanics with digital processing simplifies the overall structure while maintaining high resolution performance.
Solution Approach 2:
The patent changes the operating parameters of the ADC system by using two separate flash ADCs with different resolutions (N-bit and M-bit) instead of a single high-resolution flash ADC. This parameter change allows the system to achieve the same overall resolution with simpler individual stages, reducing the complexity of each ADC stage while maintaining the cumulative high resolution through the cascaded architecture.
Data Source
AI summary
Provided is an analog to digital converter configured to receive a continuous input signal. The analog to digital converter includes an integrating block, comprising at least an integrating stage, which output is coupled to a flash analog to digital converter. The analog to digital converter apparatus includes a feedback path coupled to the output of said flash analog to digital converter. The feedback path includes at least a digital to analog conversion block which output is compared at least to the input signal to obtain an error signal which is brought as input to said integrating block. A control block is configured to perform control comprising at least a digital integration, is coupled between the output of said flash analog to digital converter and said feedback path.